/**
* FchInitEnvUsbXhci - Config XHCI controller before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvUsbXhci (
IN VOID *FchDataPtr
)
{
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if ( LocalCfgPtr->Usb.Xhci0Enable == TRUE ) {
if ( LocalCfgPtr->Misc.S3Resume == 0 ) {
XhciInitBeforePciInit (LocalCfgPtr);
} else {
if ( !((ACPIMMIO8 (FCH_AOACx6E_USB3_D3_CONTROL) & 0x3) == 0x3)) {
if ( ACPIMMIO32 (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00) & BIT0 ) {
XhciInitIndirectReg (LocalCfgPtr);
} else {
XhciInitBeforePciInit (LocalCfgPtr);
}
}
}
} else {
//
// for power saving.
//
FchXhciPowerSavingProgram (LocalCfgPtr);
}
}
/**
* FchInitEnvUsbXhci - Config XHCI controller before PCI
* emulation
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
FchInitEnvUsbXhci (
IN VOID *FchDataPtr
)
{
UINT8 XhciEfuse;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
if ( LocalCfgPtr->Usb.Xhci1Enable == TRUE ) {
if ( LocalCfgPtr->Misc.S3Resume == 0 ) {
XhciInitBeforePciInit (LocalCfgPtr);
} else {
XhciInitIndirectReg (StdHeader);
}
} else {
//
// for power saving.
//
// add Efuse checking for Xhci enable/disable
XhciEfuse = XHCI_EFUSE_LOCATION;
GetEfuseStatus (&XhciEfuse, StdHeader);
if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) {
RwMem (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccessWidth32, 0xF0FFFBFF, 0x0);
}
}
}
