示例#1
0
void encripta(void)
{
	int bo_0 = 0;
	int bo_1 = 0;
	int bo_2 = 0;
	int bo_3 = 0;
	int config = 0;
	int i;



    printf("Teste: %d %d %d %d %d\n\r", bo_0, bo_1, bo_2, bo_3, config);
    printf("Inicializando CONFIG\n\r");
    Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x01);

    printf("\n\rConferindo Config\n\r");
    config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);
    printf("Config = %x \n\r",config);
    printf("Endereço de reg16 é 0x%x",AES_BASEADDR+CONFIG_OFFSET);

    printf("Escrevendo chave K0\n\r");
    Xil_Out32(AES_BASEADDR+BI_E_0_OFFSET,0x09cf4f3c);
    Xil_Out32(AES_BASEADDR+BI_E_1_OFFSET,0xabf71588);
    Xil_Out32(AES_BASEADDR+BI_E_2_OFFSET,0x28aed2a6);
    Xil_Out32(AES_BASEADDR+BI_E_3_OFFSET,0x2b7e1516);
    printf("Inicializando Key_Expansion\n\r");
    Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x09);

    printf("Colocando atraso...\n\r");
    for( i=0; i< 10000; i++)
    {
    	printf(".");
    }
    printf("\n\rConferindo se Key_Expansion terminou\n\r");
    config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);
    printf("Config = %x \n\r",config);

    printf("Preparando Encriptação\n\r");
    Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x08);
    printf("Escrevendo bloco de entrada 0x3243f6a8885a308d313198a2e0370734\n\r");
    Xil_Out32(AES_BASEADDR+BI_E_0_OFFSET,0xe0370734);
    Xil_Out32(AES_BASEADDR+BI_E_1_OFFSET,0x313198a2);
    Xil_Out32(AES_BASEADDR+BI_E_2_OFFSET,0x885a308d);
    Xil_Out32(AES_BASEADDR+BI_E_3_OFFSET,0x3243f6a8);
    printf("Inicializando Encriptação\n\r");
    Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x0A);
    printf("Lendo bloco encriptado\n\r");
    bo_0 = Xil_In32(AES_BASEADDR+BO_E_0_OFFSET);
    bo_1 = Xil_In32(AES_BASEADDR+BO_E_1_OFFSET);
    bo_2 = Xil_In32(AES_BASEADDR+BO_E_2_OFFSET);
    bo_3 = Xil_In32(AES_BASEADDR+BO_E_3_OFFSET);


    printf("Bo = %x %x %x %x\n\r",bo_3, bo_2, bo_1, bo_0);
    printf("Done");
}
int main()
{
	int delay;
	unsigned int inchar;
	unsigned int newlr;

    //Disable cache on OCM
    Xil_SetTlbAttributes(0xFFFF0000,0x14de2);           // S=b1 TEX=b100 AP=b11, Domain=b1111, C=b0, B=b0
    SetupIntrSystem(&IntcInstancePtr);
    print("CPU0: writing startaddress for cpu1\n\r");
    Xil_Out32(CPU1STARTADR, 0x00200000);
    dmb(); //waits until write has finished

    print("CPU0: sending the SEV to wake up CPU1\n\r");
    sev();

    while(1){

    	inchar = getchar();
    	newlr = getchar();
    	//for( delay = 0; delay < OP_DELAY; delay++)//wait
    	//{}
    	xil_printf("value %d",inchar);
    	Xil_Out8(LED_PAT,inchar);

    }

    return 0;
}
void MATRIX_MUL_IP_CORE_S_INT_G_MasterRecvWord(Xuint32 BaseAddress, Xuint32 SrcAddress)
{
  /*
   * Set user logic master control register for read transfer.
   */
  Xil_Out8(BaseAddress+MATRIX_MUL_IP_CORE_S_INT_G_MST_CNTL_REG_OFFSET, MST_SGRD);

  /*
   * Set user logic master address register to drive IP2Bus_Mst_Addr signal.
   */
  Xil_Out32(BaseAddress+MATRIX_MUL_IP_CORE_S_INT_G_MST_ADDR_REG_OFFSET, SrcAddress);

  /*
   * Set user logic master byte enable register to drive IP2Bus_Mst_BE signal.
   */
  Xil_Out16(BaseAddress+MATRIX_MUL_IP_CORE_S_INT_G_MST_BE_REG_OFFSET, 0xFFFF);

  /*
   * Start user logic master read transfer by writting special pattern to its go port.
   */
  Xil_Out8(BaseAddress+MATRIX_MUL_IP_CORE_S_INT_G_MST_GO_PORT_OFFSET, MST_START);
}
示例#4
0
int Xil_TestIO8(u8 *Addr, int Len, u8 Value)
{
	u8 ValueIn;
	int Index;

	for (Index = 0; Index < Len; Index++) {
		Xil_Out8((u32)Addr, Value);

		ValueIn = Xil_In8((u32)Addr);

		if (Value != ValueIn) {
			return -1;
		}
	}

	return 0;

}
示例#5
0
文件: xil_testio.c 项目: Akaname/Arty
s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
{
	u8 ValueIn;
	s32 Index;
	s32 Status = 0;

	for (Index = 0; Index < Length; Index++) {
		Xil_Out8((INTPTR)Addr, Value);

		ValueIn = Xil_In8((INTPTR)Addr);

		if ((Value != ValueIn) && (Status == 0)) {
			Status = -1;
			break;
		}
	}
	return Status;

}
示例#6
0
文件: main.c 项目: caiogustavo/TCC
void encripta(void)
{
    int bo_0 = 0;
    int bo_1 = 0;
    int bo_2 = 0;
    int bo_3 = 0;
    int config = 0;
    int i;
    int cnt =0;
    unsigned int key[4];

    int config1, config2, config3, config4, config5, config6, config7, config8, config9, config10;
    /*	int debug_signal_0 = 0;
    	int debug_signal_31, debug_signal_32, debug_signal_33, debug_signal_34,debug_signal_35, debug_signal_36, debug_signal_37, debug_signal_38, debug_signal_39;
    	int debug_signal_1 = 0;
    	int debug_signal_2 = 0;
    	int debug_signal_3 = 0;
    */

    key[0] = 0x09cf4f3c;
    key[1] = 0xabf71588;
    key[2] = 0x28aed2a6;
    key[3] = 0x2b7e1516;

    i = aes_expand_key(key);
    xil_printf("i = %d\n\r",i);


    /*
        xil_printf("Teste: %d %d %d %d %d\n\r", bo_0, bo_1, bo_2, bo_3, config);

        // Set config = 1
        xil_printf("Inicializando CONFIG\n\r");
        Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x10);

        // verifica config
        xil_printf("\nConferindo Config\n\r");
        config = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
        xil_printf("Config = %08x \n\r",config);
        //printf("Endereço de reg16 é 0x%08x \n",AES_BASEADDR+CONFIG_OFFSET);


        // escreve a chave e inicializa KeyExpansion
        xil_printf("Escrevendo chave K0\n\r");
        Xil_Out32(AES_BASEADDR+BI_E_0_OFFSET,0x09cf4f3c);
        Xil_Out32(AES_BASEADDR+BI_E_1_OFFSET,0xabf71588);
        Xil_Out32(AES_BASEADDR+BI_E_2_OFFSET,0x28aed2a6);
        Xil_Out32(AES_BASEADDR+BI_E_3_OFFSET,0x2b7e1516);


        xil_printf("Inicializando Key_Expansion\n\r");
        Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x11);

        xil_printf("Colocando atraso...\n\r");
        //while( config == 0xca10d009 )

        xil_printf("\n\rConferindo se Key_Expansion terminou\n\r");
        config = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
        xil_printf("Config = %08x \n\r",config);
    */
    xil_printf("Preparando Encriptação\n\r");
    Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x01);
    xil_printf("Escrevendo bloco de entrada 0x3243f6a8885a308d313198a2e0370734\n\r");
    Xil_Out32(AES_BASEADDR+BI_E_0_OFFSET,0xe0370734);
    Xil_Out32(AES_BASEADDR+BI_E_1_OFFSET,0x313198a2);
    Xil_Out32(AES_BASEADDR+BI_E_2_OFFSET,0x885a308d);
    Xil_Out32(AES_BASEADDR+BI_E_3_OFFSET,0x3243f6a8);
    xil_printf("Inicializando Encriptação\n\r");
    Xil_Out8(AES_BASEADDR+CONFIG_1_OFFSET,0x01);

    config = Xil_In8(AES_BASEADDR+CONFIG_3_OFFSET);

    while ( config != 3)
    {
        config = Xil_In8(AES_BASEADDR+CONFIG_3_OFFSET);
        cnt++;
    }

    xil_printf("contador = %d\n\r",cnt);

    config1 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);

    config2 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
    config3 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
    config4 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
    config5 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);

    config6 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
    config7 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
    config8 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
    config9 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
    config10 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);

    xil_printf("Config1 = %08x \n\r",config1);
    xil_printf("Config2 = %08x \n\r",config2);
    xil_printf("Config3 = %08x \n\r",config3);
    xil_printf("Config4 = %08x \n\r",config4);
    xil_printf("Config5 = %08x \n\r",config5);
    xil_printf("Config6 = %08x \n\r",config6);
    xil_printf("Config7 = %08x \n\r",config7);
    xil_printf("Config8 = %08x \n\r",config8);
    xil_printf("Config9 = %08x \n\r",config9);
    xil_printf("Config10 = %08x \n\r",config10);

    for( i=0; i<2; i++)
    {
        //xil_printf("Conferindo Sinais Internos\n\r");
        //config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);
        //xil_printf("Config = %08x \n\r",config);

        /*    	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_S0);
            	//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
            	//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
            	//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
            	debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_34 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_35 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_36 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_37 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_38 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_39 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);

            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_31);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_32);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_33);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_34);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_35);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_36);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_37);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_38);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_39);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_0);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_1);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_2);

            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
            	//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
            	//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
            	//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
            	debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
            	debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z1);
            	debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z2);
            	debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z3);
            	debug_signal_34 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z4);
            	debug_signal_35 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
            	debug_signal_36 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_37 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
            	debug_signal_38 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_39 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);

            	xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
            	xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_31);
            	xil_printf("z1 = %08x __ ___ ___ __\n\r",debug_signal_32);
            	xil_printf("z2 = %08x __ ___ ___ __\n\r",debug_signal_33);
            	xil_printf("z3 = %08x __ ___ ___ __\n\r",debug_signal_34);
            	xil_printf("z4 = %08x __ ___ ___ __\n\r",debug_signal_35);
            	xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_36);
            	xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_37);
            	xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_38);
            	xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_39);
            	xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_0);
            	xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_1);
            	xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_2);


            	//config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);

            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
            	//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
            	//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
            	//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
            	debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	xil_printf("k2 = %08x __ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);

            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
            	//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
            	//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
            	//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
            	debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);

            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
            	//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
            	//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
            	//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
            	debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);

                //xil_printf("Config = %08x \n\r",config);
        */
        xil_printf("Lendo bloco encriptado\n\r");
        bo_0 = Xil_In32(AES_BASEADDR+BO_E_0_OFFSET);
        bo_1 = Xil_In32(AES_BASEADDR+BO_E_1_OFFSET);
        bo_2 = Xil_In32(AES_BASEADDR+BO_E_2_OFFSET);
        bo_3 = Xil_In32(AES_BASEADDR+BO_E_3_OFFSET);
        xil_printf("Bo_e = %x %x %x %x\n\r",bo_3, bo_2, bo_1, bo_0);

        /*        xil_printf("Reinicializando Encriptação\n\r");
                Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x08);
                Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x0A);
        */

        //xil_printf("-----------------------------------------\n\r");
    }

//    xil_printf("Preparando Decriptação\n\r");
//    Xil_Out8(AES_BASEADDR+CONFIG_1_OFFSET,0x01);
    xil_printf("Escrevendo bloco de entrada bo_e\n\r");
    Xil_Out32(AES_BASEADDR+BI_D_0_OFFSET,bo_0);
    Xil_Out32(AES_BASEADDR+BI_D_1_OFFSET,bo_1);
    Xil_Out32(AES_BASEADDR+BI_D_2_OFFSET,bo_2);
    Xil_Out32(AES_BASEADDR+BI_D_3_OFFSET,bo_3);
    xil_printf("Lendo bloco escrito para decriptação\n\r");
    bo_0 = Xil_In32(AES_BASEADDR+BO_D_0_OFFSET);
    bo_1 = Xil_In32(AES_BASEADDR+BO_D_1_OFFSET);
    bo_2 = Xil_In32(AES_BASEADDR+BO_D_2_OFFSET);
    bo_3 = Xil_In32(AES_BASEADDR+BO_D_3_OFFSET);
    xil_printf("Bo_e = %x %x %x %x\n\r",bo_3, bo_2, bo_1, bo_0);


    xil_printf("Inicializando Decriptação\n\r");
    Xil_Out8(AES_BASEADDR+CONFIG_2_OFFSET,0x01);

    for( i=0; i<2; i++)
    {
        //xil_printf("Conferindo Sinais Internos\n\r");
        //config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);
        //xil_printf("Config = %08x \n\r",config);

        /*    	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_S0);
            	//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
            	//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
            	//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
            	debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_34 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_35 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_36 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_37 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_38 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_39 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);

            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_31);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_32);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_33);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_34);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_35);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_36);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_37);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_38);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_39);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_0);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_1);
            	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_2);

            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
            	//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
            	//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
            	//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
            	debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
            	debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z1);
            	debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z2);
            	debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z3);
            	debug_signal_34 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z4);
            	debug_signal_35 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
            	debug_signal_36 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_37 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
            	debug_signal_38 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_39 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);

            	xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
            	xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_31);
            	xil_printf("z1 = %08x __ ___ ___ __\n\r",debug_signal_32);
            	xil_printf("z2 = %08x __ ___ ___ __\n\r",debug_signal_33);
            	xil_printf("z3 = %08x __ ___ ___ __\n\r",debug_signal_34);
            	xil_printf("z4 = %08x __ ___ ___ __\n\r",debug_signal_35);
            	xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_36);
            	xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_37);
            	xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_38);
            	xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_39);
            	xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_0);
            	xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_1);
            	xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_2);


            	//config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);

            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
            	//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
            	//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
            	//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
            	debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	xil_printf("k2 = %08x __ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);

            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
            	//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
            	//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
            	//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
            	debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);

            	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
            	//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
            	//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
            	//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
            	debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
            	xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);

                //xil_printf("Config = %08x \n\r",config);
        */
        xil_printf("Lendo bloco decriptado\n\r");
        bo_0 = Xil_In32(AES_BASEADDR+BO_D_0_OFFSET);
        bo_1 = Xil_In32(AES_BASEADDR+BO_D_1_OFFSET);
        bo_2 = Xil_In32(AES_BASEADDR+BO_D_2_OFFSET);
        bo_3 = Xil_In32(AES_BASEADDR+BO_D_3_OFFSET);
        xil_printf("Bo_d = %x %x %x %x\n\r",bo_3, bo_2, bo_1, bo_0);

        /*        xil_printf("Reinicializando Encriptação\n\r");
                Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x08);
                Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x0A);
        */

        //xil_printf("-----------------------------------------\n\r");
    }

    xil_printf("Lendo config\n\r");
    config = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
    xil_printf("Config = %8x\n\r",config);

    /*
    	Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_S0);
    	//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
    	//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
    	//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
    	debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
    	debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
    	debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
    	debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);

    	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
    	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_31);
    	xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_32);
    	xil_printf("s0 = %08x __ ___ ___ __\n\r\n\r",debug_signal_33);


        xil_printf("Lendo bloco encriptado\n\r");
        bo_0 = Xil_In32(AES_BASEADDR+BO_E_0_OFFSET);
        bo_1 = Xil_In32(AES_BASEADDR+BO_E_1_OFFSET);
        bo_2 = Xil_In32(AES_BASEADDR+BO_E_2_OFFSET);
        bo_3 = Xil_In32(AES_BASEADDR+BO_E_3_OFFSET);


        xil_printf("Bo = %x %x %x %x\n\r",bo_3, bo_2, bo_1, bo_0);
        */
    xil_printf("Done\n\r");
}
/******************************************************************************
* This function reads a number of bytes from an IIC chip into a
* specified buffer.
*
* @param    ChipAddress contains the address of the IIC core.
* @param    RegAddress contains the address of the register to write to.
* @param    pBuffer contains the address of the data buffer to be filled.
* @param    ByteCount contains the number of bytes in the buffer to be read.
*           This value is constrained by the page size of the device such
*           that up to 64K may be read in one call.
*
* @return   The number of bytes read. A value less than the specified input
*           value indicates an error.
*
* @note     None.
*
******************************************************************************/
int zed_iic_axi_IicRead(zed_iic_t *pIIC, Xuint8 ChipAddress, Xuint8 RegAddress, 
                                         Xuint8 *pBuffer, Xuint8 ByteCount)
{
  Xuint8 ReceivedByteCount = 0;
  Xuint8 SentByteCount = 0;
  Xuint8 ControlReg;
  Xuint8 StatusReg;
  int cnt = 0;
  zed_iic_axi_t *pContext = (zed_iic_axi_t *)(pIIC->pContext);

#if 1
  // Make sure all the Fifo's are cleared and Bus is Not busy.
  do
  {
    StatusReg = Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET);
    //xil_printf("[%s] Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET) => 0x%02X\n\r", pContext->szName, StatusReg );
    StatusReg = StatusReg & (XIIC_SR_RX_FIFO_EMPTY_MASK |
	                          XIIC_SR_TX_FIFO_EMPTY_MASK |
                             XIIC_SR_BUS_BUSY_MASK);
    if ((StatusReg & XIIC_SR_RX_FIFO_EMPTY_MASK) != XIIC_SR_RX_FIFO_EMPTY_MASK)
    {
      /*
       * The RX buffer is not empty and it is assumed there is a stale
       * message in there.  Attempt to clear out the RX buffer, otherwise
       * this loop spins forever.
       */
      XIic_ReadReg(pContext->CoreAddress, XIIC_DRR_REG_OFFSET);
    }

	/*
	 * Check to see if the bus is busy.  Since we are master, if the bus is
	 * still busy that means that arbitration has been lost.
	 *
	 * According to Product Guide PG090, October 16, 2012:
	 *
	 * Control Register (0x100), Bit 2 MSMS:
	 *
	 * "Master/Slave Mode Select. When this bit is changed from 0 to 1,
	 * the AXI IIC bus interface generates a START condition in master
	 * mode. When this bit is cleared, a STOP condition is generated and
	 * the AXI IIC bus interface switches to slave mode. When this bit is
	 * cleared by the hardware, because arbitration for the bus has been
	 * lost, a STOP condition is not generated. (See also Interrupt(0):
	 * Arbitration Lost in Chapter 3.)"
	 *
	 * According to this, it should be okay to clear the master/slave mode
	 * select to clear a false start condition with a stop and regain
	 * arbitration over the bus.
	 */
    if ((StatusReg & XIIC_SR_BUS_BUSY_MASK) == XIIC_SR_BUS_BUSY_MASK)
    {
    	ControlReg = Xil_In8(pContext->CoreAddress + XIIC_CR_REG_OFFSET);
    	ControlReg = ControlReg & 0xFB;  // Clear the MSMS bit.
    	Xil_Out8(pContext->CoreAddress + XIIC_CR_REG_OFFSET, ControlReg);
    }
  } while (StatusReg != (XIIC_SR_RX_FIFO_EMPTY_MASK |
			                XIIC_SR_TX_FIFO_EMPTY_MASK));
#endif

  // Position the Read pointer to specific location.
  do
  {
    StatusReg = Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET);
    //xil_printf("[%s] Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET) => 0x%02X\n\r", pContext->szName, StatusReg );
    if(!(StatusReg & XIIC_SR_BUS_BUSY_MASK))
    {
      SentByteCount = XIic_DynSend(pContext->CoreAddress, ChipAddress, 
                                  (Xuint8 *)&RegAddress, 1,
    								        XIIC_REPEATED_START);
    }
    cnt++;
  }while(SentByteCount != 1 && (cnt < 100));
  
  // Error writing chip address so return SentByteCount
  if (SentByteCount < 1) { return SentByteCount; }

  // Receive the data.
  ReceivedByteCount = XIic_DynRecv(pContext->CoreAddress, ChipAddress, pBuffer, 
                                   ByteCount);

  // Return the number of bytes received.
  return ReceivedByteCount;
}
示例#8
0
// begin the transfer
void my_dma_controller_start_transfer() {
	  Xil_Out16(XPAR_MY_DMA_0_BASEADDR+MY_DMA_MST_BE_REG_OFFSET, 0xFFFF);
	  Xil_Out8(XPAR_MY_DMA_0_BASEADDR+MY_DMA_MST_GO_PORT_OFFSET, MST_START);

}
示例#9
0
int axi_write8(uint32_t addr, uint8_t val) {
	Xil_Out8(offset + addr,val);
 	return  1;
}
示例#10
0
int main(void) {

    u8  c;

    while(1) {

    	c=XUartLite_RecvByte(uartReadReg);

    	switch(c) {

    		//-------------------------------------------------
    		// Reply with the help menu
    		//-------------------------------------------------
    		case '?':
    			xil_printf("--------------------------\r\n");
    			xil_printf("	count Q = %x\r\n",Xil_In16(countQReg));
    			xil_printf("--------------------------\r\n");
    			xil_printf("?: help menu\r\n");
    			xil_printf("o: k\r\n");
    			xil_printf("c: COUNTER	count up LEDs (by 9)\r\n");
    			xil_printf("l: COUNTER	load counter\r\n");
    			xil_printf("r: COUNTER	reset counter\r\n");
    			xil_printf("f: flush terminal\r\n");
    			break;

    		//-------------------------------------------------
    		// Basic I/O loopback
    		//-------------------------------------------------
    		case 'o':
    			xil_printf("k \r\n");
    			break;

    		//-------------------------------------------------
    		// Tell the counter to count up
    		//-------------------------------------------------
    		case 'c':
    			Xil_Out8(countCtrlReg,count_COUNT);
    			Xil_Out8(countCtrlReg,count_HOLD);
    			break;

        	//-------------------------------------------------
        	// Tell the counter to load a value
        	//-------------------------------------------------
        	case 'l':
        		xil_printf("Enter a 0-9 value to store in the counter: ");
            	c=XUartLite_RecvByte(uartReadReg) - 0x30;
        		Xil_Out8(countQReg,c);					// put value into slv_reg1
        		Xil_Out8(countCtrlReg,count_LOAD);				// load command
    			xil_printf("%c\r\n",c+0x30);
        		break;

            //-------------------------------------------------
            // Reset the counter
            //-------------------------------------------------
            case 'r':
            	Xil_Out8(countCtrlReg,count_RESET);				// reset command
            	break;

            //-------------------------------------------------
            // Clear the terminal window
            //-------------------------------------------------
            case 'f':
            	for (c=0; c<40; c++) xil_printf("\r\n");
               	break;

          //-------------------------------------------------
          // Unknown character was
          //-------------------------------------------------
    		default:
    			xil_printf("unrecognized character: %c\r\n",c);
    			break;
    	} // end case
    } // end while 1
    return 0;
} // end main
示例#11
0
文件: main.c 项目: cbusho/Lab4_Busho
int main(void)
{
 while (1)
 {
	 unsigned char c, d, e;
	 c = 0x00;
	 d = 0x00;
	 e = 0x00;

	 while(c == 0x00){
		 c = XUartLite_RecvByte(0x84000000); //receive letter
	 }
	 XUartLite_SendByte(0x84000000, c);

	 while(d == 0x00){
		 d = XUartLite_RecvByte(0x84000000); //receive letter
	 }
	 XUartLite_SendByte(0x84000000, d);

	 while(e == 0x00){
		 e = XUartLite_RecvByte(0x84000000); //receive letter
	 }
	 XUartLite_SendByte(0x84000000, e);
	 XUartLite_SendByte(0x84000000, 0x20);	 //send space char

	 //led command
	 if((c == 0x6C) && (d == 0x65) && (e == 0x64)){
		 c = 0x00;
		 d = 0x00;
		 e = 0x00;

		 while(c == 0x00){
		 	 c = XUartLite_RecvByte(0x84000000) - 0x30; //receive letter
		 	 d = c - 0x27;
		 	 if((c >= 0x0) && (c <= 0x9)){
		 		 e = c;
		 	 }
		 	 else if((d >= 0xA) && (d <= 0xF)){
		 		 e = d;
		 	 }
		 	 else{
		 		 e = 0x0;
		 	 }
		 }
		 XUartLite_SendByte(0x84000000, c + 0x30);
		 e = e << 4;

		 c = 0x00;
		 d = 0x00;

		 while(c == 0x00){
			 c = XUartLite_RecvByte(0x84000000) - 0x30; //receive letter
			 d = c - 0x27;
			 if((c >= 0x0) && (c <= 0x9)){
				 e += c;
			 }
			 else if((d >= 0xA) && (d <= 0xF)){
				 e += d;
			 }
			 else{
				 e = e;
			 }
		 }
		 XUartLite_SendByte(0x84000000, c + 0x30);
		 Xil_Out8(0x83000000, e);

	 }

	 //switch command
	 if((c == 0x73) && (d == 0x77) && (e == 0x74)){
		 c = 0x00;
		 d = 0x00;
		 e = 0x00;

		 c = Xil_In8(0x83000004) & 0xF;
		 d = Xil_In8(0x83000004) & 0xF0;

		 d = d >> 4;

		 if(c <= 0x9){
			 c = c + 0x30;
		 }
		 else{
			 c = c + 0x57;
		 }

		 if(d <= 0x9){
			 d = d + 0x30;
		 }
		 else{
			 d = d + 0x57;
		 }

		 XUartLite_SendByte(0x84000000, d);
		 XUartLite_SendByte(0x84000000, c);

	 }

	 XUartLite_SendByte(0x84000000, 0xA);	 //send new line char
	 XUartLite_SendByte(0x84000000, 0xD);	 //send return char

 }
示例#12
0
int main() {
  Xil_L1DCacheDisable();
  Xil_L2CacheDisable();
  disable_caches();

  int h, j, i;
  vdma_handle handle;
  sepimgfilter_handle filter_handle;
  char img[] = {0, 0, 0, 0, 1, 1, 1, 0, 2, 2, 2, 0, 3, 3, 3, 0, 4, 4, 4, 0, 5, 5, 5, 0, 6, 6, 6, 0, 7, 7, 7, 0, 8, 8, 8, 0, 9, 9, 9, 0, 10, 10, 10, 0, 11, 11, 11, 0, 12, 12, 12, 0, 13, 13, 13, 0, 14, 14, 14, 0, 15, 15, 15, 0};
  unsigned char hz_coeffs[] = {1, 4, 7, 4, 1};
  unsigned char vt_coeffs[] = {1, 4, 7, 4, 1};
  unsigned int norm = 289;

  int size=64, width=8, height=8;
  unsigned char *img_data;
  unsigned char *img_info;

  int frame_len = 1 * width * height;


  init_platform();
  xil_printf("\r\n\nHelloworld application\r\n");
  xil_printf("Setting I/O buffers\r\n");

  // memset input buffer 1
  for(i=0; i<size; i++){
	  Xil_Out8(MEM2VDMA_BUFFER1_BASEADDR + i, img[i]);
  }
  // memset input buffer 2
  for(i=0; i<BUFFER_SIZE/4; i++) Xil_Out32(MEM2VDMA_BUFFER2_BASEADDR + i*4, 0xBBBBBBBB);
  // memset input buffer 3
  for(i=0; i<BUFFER_SIZE/4; i++) Xil_Out32(MEM2VDMA_BUFFER3_BASEADDR + i*4, 0xCCCCCCCC);
  // memset output buffer 1
  for(i=0; i<BUFFER_SIZE/4; i++) Xil_Out32(VDMA2MEM_BUFFER1_BASEADDR + i*4, 0xFFFFFFFF);
  // memset output buffer 2
  for(i=0; i<BUFFER_SIZE/4; i++) Xil_Out32(VDMA2MEM_BUFFER2_BASEADDR + i*4, 0xFFFFFFFF);
  // memset output buffer 3
  for(i=0; i<BUFFER_SIZE/4; i++) Xil_Out32(VDMA2MEM_BUFFER3_BASEADDR + i*4, 0xFFFFFFFF);

  xil_printf("Setting VDMA registers\r\n");

  //vdma_setup(&handle, page_size, AXI_VDMA_BASEADDR, width, height, PIXEL_CHANNELS, BUFFER_SIZE, MEM2VDMA_BUFFER1_BASEADDR, MEM2VDMA_BUFFER2_BASEADDR, MEM2VDMA_BUFFER3_BASEADDR, VDMA2MEM_BUFFER1_BASEADDR, VDMA2MEM_BUFFER2_BASEADDR, VDMA2MEM_BUFFER3_BASEADDR, AXI_PULSER_ADDR);
  handle.baseAddr = AXI_VDMA_BASEADDR;
  handle.width = 8;
  handle.height = 8;
  handle.pixelChannels = 1;
  handle.fbLength = handle.width * handle.height * handle.pixelChannels;
  handle.fb1PhysicalAddress_mm2s = 0x1f400000;
  handle.fb2PhysicalAddress_mm2s = 0x1f500000;
  handle.fb3PhysicalAddress_mm2s = 0x1f600000;
  handle.fb1PhysicalAddress_s2mm = 0x1f700000;
  handle.fb2PhysicalAddress_s2mm = 0x1f800000;
  handle.fb3PhysicalAddress_s2mm = 0x1f900000;
  handle.pulserPhysicalAddress   = 0x46000000;

  filter_handle.baseAddr = AXI_SEPIMGFILTER;


  xil_printf("Setting sepImageFilter registers\r\n");
  //sepImageFilter_setup_handle(&filter_handle, &handle.vdmaHandler, page_size, AXI_SEPIMGFILTER);

  sepImageFilter_setImageParams(&filter_handle, width, height);
  sepImageFilter_setHzKernelCoeffs(&filter_handle, hz_coeffs[0], hz_coeffs[1], hz_coeffs[2], hz_coeffs[3], hz_coeffs[4]);
  sepImageFilter_setVtKernelCoeffs(&filter_handle, vt_coeffs[0], vt_coeffs[1], vt_coeffs[2], vt_coeffs[3], vt_coeffs[4]);
  sepImageFilter_setNormalizationFactor(&filter_handle, norm);
  sepImageFilter_setup(&filter_handle);

  xil_printf("Setting up done.\r\n");

  xil_printf("Starting VDMA triple buffering..\r\n");
  //xil_printf("sepImageFilter status register: %d\r\n", Xil_In32(0x47000000));

  sepImageFilter_start(&filter_handle);
  vdma_start_triple_buffering_mod(&handle);
  //while(1);
  //xil_printf("Starting sepImageFilter..\r\n");


  //xil_printf("VDMA and filter started.\r\n");

  // Read the image



  //xil_printf("sepImageFilter status register: %d\r\n", Xil_In32(0x47000000));

  // wait for filter to finish
  //xil_printf("Waiting the filter to finish: %d\r\n", sepImageFilter_running(&filter_handle) == 1);
  while(sepImageFilter_running(&filter_handle) != 0);

  //dcache_clean();

  xil_printf("Print input buffer (0x%x):\r\n", handle.fb1PhysicalAddress_mm2s);
	for(i=0; i<size; i++) xil_printf("[0x%x] 0x%x\r\n", handle.fb1PhysicalAddress_mm2s + (i<<2), Xil_In32(handle.fb1PhysicalAddress_mm2s + (i<<2)));
	xil_printf("\r\n\n");

	xil_printf("Print output buffer (0x%x):\r\n", handle.fb2PhysicalAddress_mm2s);
	for(i=0; i<size; i++) xil_printf("[0x%x] 0x%x\r\n", handle.fb2PhysicalAddress_mm2s + (i<<2), Xil_In32(handle.fb2PhysicalAddress_mm2s + (i<<2)));
	xil_printf("\r\n\n");

	xil_printf("Print output buffer (0x%x):\r\n", handle.fb3PhysicalAddress_mm2s);
	for(i=0; i<size; i++) xil_printf("[0x%x] 0x%x\r\n", handle.fb3PhysicalAddress_mm2s + (i<<2), Xil_In32(handle.fb3PhysicalAddress_mm2s + (i<<2)));


  xil_printf("\n\n\r**********************************\r\n");
  xil_printf("Print output buffer (0x%x):\r\n", handle.fb1PhysicalAddress_s2mm);
  for(i=0; i<size; i++) xil_printf("[0x%x] 0x%x\r\n", handle.fb1PhysicalAddress_s2mm + (i<<2), Xil_In32(handle.fb1PhysicalAddress_s2mm + (i<<2)));
  xil_printf("\r\n\n");

  xil_printf("Print output buffer (0x%x):\r\n", handle.fb2PhysicalAddress_s2mm);
  for(i=0; i<size; i++) xil_printf("[0x%x] 0x%x\r\n", handle.fb2PhysicalAddress_s2mm + (i<<2), Xil_In32(handle.fb2PhysicalAddress_s2mm + (i<<2)));
  xil_printf("\r\n\n");

  xil_printf("Print output buffer (0x%x):\r\n", handle.fb3PhysicalAddress_s2mm);
  for(i=0; i<size; i++) xil_printf("[0x%x] 0x%x\r\n", handle.fb3PhysicalAddress_s2mm + (i<<2), Xil_In32(handle.fb3PhysicalAddress_s2mm + (i<<2)));
  xil_printf("\r\n\n");

  xil_printf("Bye!\r\n");

  xil_printf("sepImageFilter status register: %d\r\n", Xil_In32(0x47000000));

  while(1);


  cleanup_platform();
  return 0;
}