void gbusters_main_write(unsigned short address, unsigned char data)
{
switch (address)
{
case 0x1f80:
set_ram_bank(data);
return;
case 0x1f84:
*soundlatch = data;
return;
case 0x1f88:
ZetSetVector(0xff);
ZetSetIRQLine(0, ZET_IRQSTATUS_ACK);
return;
case 0x1f8c:
// watchdog
return;
case 0x1f98:
K052109RMRDLine = data & 0x01;
return;
}
if ((address & 0xc000) == 0x0000) {
K052109_051960_w(address & 0x3fff, data);
return;
}
}
static void __fastcall gradius3_main_write_byte(UINT32 address, UINT8 data)
{
if ((address & 0xfe0000) == 0x180000) {
DrvShareRAM2[(address & 0x1ffff)^1] = data;
expand_graphics_single(address);
return;
}
switch (address)
{
case 0x0c0000:
case 0x0c0001:
{
// if enabling CPU B, burn off some cycles to keep things sync'd.
if (gradius3_cpub_enable & 8 && ~data & 8) {
INT32 cycles_to_burn = SekTotalCycles();
SekClose();
SekOpen(1);
SekIdle(cycles_to_burn - SekTotalCycles());
SekClose();
SekOpen(0);
}
gradius3_priority =(data & 0x04)>>2;
gradius3_cpub_enable = data & 0x08;
irqA_enable = data & 0x20;
}
return;
case 0x0d8000:
case 0x0d8001:
interrupt_triggered = irqB_mask & 0x04;
return;
case 0x0e0000:
case 0x0e0001:
// watchdog
return;
case 0x0e8000:
*soundlatch = data;
return;
case 0x0f0000:
ZetSetVector(0xff);
ZetSetIRQLine(0, CPU_IRQSTATUS_ACK);
return;
}
if (address >= 0x14c000 && address <= 0x153fff) {
address -= 0x14c000;
K052109Write(address / 2, data);
return;
}
}
void bottom9_main_write(unsigned short address, unsigned char data)
{
switch (address)
{
case 0x1f80:
bankswitch(data);
return;
case 0x1f90:
{
K052109RMRDLine = data & 0x04;
bottom9_video_enable = ~data & 0x08;
zoomreadroms = data & 0x10;
K052109_selected = data & 0x20;
}
return;
case 0x1fa0:
// watchdog
return;
case 0x1fb0:
*soundlatch = data;
return;
case 0x1fc0:
ZetSetVector(0xff);
ZetSetIRQLine(0, ZET_IRQSTATUS_ACK);
return;
}
if ((address & 0xfff0) == 0x1ff0) {
K051316WriteCtrl(0, address & 0x0f, data);
return;
}
if (K052109_selected == 0) {
if ((address & 0xf800) == 0x0000) {
K051316Write(0, address & 0x7ff, data);
return;
}
if ((address & 0xf800) == 0x2000) {
DrvPalRAM[address & 0x7ff] = data;
return;
}
}
if ((address & 0xc000) == 0x0000) {
K052109_051960_w(address & 0x3fff, data);
return;
}
}
void parodius_main_write(UINT16 address, UINT8 data)
{
switch (address)
{
case 0x3fc0:
K052109RMRDLine = data & 0x08;
return;
case 0x3fc4:
nDrvRomBank[1] = data;
return;
case 0x3fc8:
ZetSetVector(0xff);
ZetSetIRQLine(0, ZET_IRQSTATUS_ACK);
return;
case 0x3fcc:
case 0x3fcd:
K053260Write(0, address & 1, data);
return;
}
if ((address & 0xf800) == 0x0000) {
if (nDrvRomBank[1] & 1) {
DrvPalRAM[((nDrvRomBank[1] & 0x04) << 9) + address] = data;
} else {
DrvBankRAM[address] = data;
}
return;
}
if ((address & 0xfff0) == 0x3fa0) {
K053244Write(0, address & 0x0f, data);
return;
}
if ((address & 0xfff0) == 0x3fb0) {
K053251Write(address & 0x0f, data);
return;
}
if ((address & 0xf800) == 0x2000) {
if (nDrvRomBank[1] & 0x02) {
K053245Write(0, address & 0x7ff, data);
return;
}
}
if (address >= 0x2000 && address <= 0x5fff) {
K052109Write(address - 0x2000, data);
}
}
void __fastcall gradius3_main_write_byte(unsigned int address, unsigned char data)
{
switch (address)
{
case 0x0c0000:
case 0x0c0001:
{
// if enabling CPU B, burn off some cycles to keep things sync'd.
if (gradius3_cpub_enable & 8 && ~data & 8) {
int cycles_to_burn = SekTotalCycles();
SekClose();
SekOpen(1);
SekIdle(cycles_to_burn - SekTotalCycles());
SekClose();
SekOpen(0);
}
gradius3_priority = data & 0x04;
gradius3_cpub_enable = data & 0x08;
irqA_enable = data & 0x20;
}
return;
case 0x0d8000:
case 0x0d8001:
interrupt_triggered = irqB_mask & 0x04;
return;
case 0x0e0000:
case 0x0e0001:
// watchdog
return;
case 0x0e8000:
*soundlatch = data;
return;
case 0x0f0000:
ZetSetVector(0xff);
ZetSetIRQLine(0, ZET_IRQSTATUS_ACK);
return;
}
if (address >= 0x14c000 && address <= 0x153fff) {
address -= 0x14c000;
K052109Write(address / 2, data);
return;
}
}
void crimfght_main_write(UINT16 address, UINT8 data)
{
switch (address)
{
case 0x3f8c:
*soundlatch = data;
ZetSetVector(0xff);
ZetSetIRQLine(0, ZET_IRQSTATUS_ACK);
break;
}
if (address >= 0x2000 && address <= 0x5fff) {
K052109_051960_w(address - 0x2000, data);
return;
}
}
void rollerg_main_write(unsigned short address, unsigned char data)
{
switch (address)
{
case 0x0010:
readzoomroms = data & 0x04;
K051316WrapEnable(0, data & 0x20);
return;
case 0x0020:
// watchdog
return;
case 0x0030:
case 0x0031:
K053260Write(0, address & 1, data);
return;
case 0x0040:
ZetSetVector(0xff);
// ZetRaiseIrq(0);
ZetSetIRQLine(0, ZET_IRQSTATUS_ACK);
return;
}
if ((address & 0xfff0) == 0x0200) {
K051316WriteCtrl(0, address & 0x0f, data);
return;
}
if ((address & 0xfff0) == 0x0300) {
K053244Write(0, address & 0x0f, data);
return;
}
if ((address & 0xf800) == 0x0800) {
K051316Write(0, address & 0x7ff, data);
return;
}
if ((address & 0xf800) == 0x1000) {
K053245Write(0, address & 0x7ff, data);
return;
}
}
void rollerg_main_write(UINT16 address, UINT8 data)
{
switch (address)
{
case 0x0010:
readzoomroms = data & 0x04;
K051316WrapEnable(0, data & 0x20);
return;
case 0x0020:
// watchdog
return;
case 0x0030:
case 0x0031:
K053260Write(0, address & 1, data);
return;
case 0x0040:
ZetSetVector(0xff);
ZetSetIRQLine(0, CPU_IRQSTATUS_ACK);
return;
}
if ((address & 0xfff0) == 0x0200) {
K051316WriteCtrl(0, address & 0x0f, data);
return;
}
if ((address & 0xfff0) == 0x0300) {
K053244Write(0, address & 0x0f, data);
return;
}
if ((address & 0xf800) == 0x0800) {
K051316Write(0, address & 0x7ff, data);
return;
}
if ((address & 0xf800) == 0x1000) {
K053245Write(0, address & 0x7ff, data);
return;
}
}
void aliens_main_write(UINT16 address, UINT8 data)
{
switch (address)
{
case 0x5f88:
set_ram_bank(data & 0x20);
K052109RMRDLine = data & 0x40;
return;
case 0x5f8c:
*soundlatch = data;
ZetSetVector(0xff);
ZetSetIRQLine(0, ZET_IRQSTATUS_ACK);
//ZetRaiseIrq(0xff);
return;
}
if ((address & 0xc000) == 0x4000) {
K052109_051960_w(address & 0x3fff, data);
return;
}
}
