static conv_method AskHow( type_class_def fr, type_class_def to ) /********************************************************************/ { if( _FPULevel( FPU_87 ) ) { return( FPCvtTable[fr + to * XX] ); } else { return( CvtTable[fr + to * XX] ); } }
void InitRegTbl( void ) /********************************* Initialize the tables. */ { if( _FPULevel( FPU_87 ) ) { HW_CAsgn( STParmReg[Max87Stk], HW_EMPTY ); } if( _IsTargetModel( INDEXED_GLOBALS ) ) { HW_CAsgn( FPParm2Reg[0], HW_ECX_ESI ); } else { HW_CAsgn( FPParm2Reg[0], HW_ECX_EBX ); } }
static conv_method AskHow( type_class_def fr, type_class_def to ) /********************************************************************* return the conversion method required to convert from "fr" to "to" */ { if( to == XX || fr == XX ) { /* special case for 64 bit operand of IDIV */ return( BAD ); } if( _FPULevel( FPU_87 ) ) { return( FPCvtTable[fr + to * XX] ); } else { return( CvtTable[fr + to * XX] ); } }
extern byte CondCode( instruction *cond ) { /********************************************** Return the condition code number for the encoding, associated with "cond" */ issigned is_signed; if( _FPULevel( FPU_87 ) ) { is_signed = SIGNED_87; } else { is_signed = SIGNED_86; } if( is_signed & Signed[cond->type_class] ) { return( SCondTable[cond->head.opcode - FIRST_CONDITION] ); } else { return( UCondTable[cond->head.opcode - FIRST_CONDITION] ); } }
void UpdateReturn( call_state *state, type_def *tipe, type_class_def type_class, aux_handle aux ) /**************************************************************************************************/ { hw_reg_set normal; if( _FPULevel( FPU_87 ) && _NPX( state->attr ) && (tipe->attr & TYPE_FLOAT) ) { HW_COnlyOn( state->return_reg, HW_ST0 ); } else { HW_CTurnOff( state->return_reg, HW_FLTS ); } if( tipe == TypeNone ) { if( HW_CEqual( state->return_reg, HW_EMPTY ) ) return; FEMessage( MSG_BAD_RETURN_REGISTER, aux ); HW_CAsgn( state->return_reg, HW_EMPTY ); state->attr &= ~ROUTINE_HAS_SPECIAL_RETURN; } else if( type_class == XX ) { normal = ReturnReg( WD, _NPX( state->attr ) ); if( HW_Equal( state->return_reg, normal ) ) return; if( HW_CEqual( state->return_reg, HW_EMPTY ) ) return; // if( !HW_Ovlap( state->return_reg, state->unalterable ) && // IsRegClass( state->return_reg, WD ) ) // return; if( IsRegClass( state->return_reg, WD ) ) return; FEMessage( MSG_BAD_RETURN_REGISTER, aux ); state->return_reg = normal; state->attr &= ~ROUTINE_HAS_SPECIAL_RETURN; } else { normal = ReturnReg( type_class, _NPX( state->attr ) ); if( HW_Equal( state->return_reg, normal ) ) return; // if( !HW_Ovlap( state->return_reg, state->unalterable ) && // IsRegClass( state->return_reg, type_class ) ) // return; if( IsRegClass( state->return_reg, type_class ) ) return; FEMessage( MSG_BAD_RETURN_REGISTER, aux ); state->return_reg = normal; state->attr &= ~ROUTINE_HAS_SPECIAL_RETURN; } }