int macx_trapfpe_() { fpu_control_t mode, mode_sse; _FPU_GETCW (mode) ; mode &= (_FPU_RESERVED | _FE_DIVBYZERO | _FE_OVERFLOW | _FE_INVALID) ; _FPU_SETCW (mode) ; _FPU_GETMXCSR (mode_sse) ; mode_sse &= (0xFFFF0000 | (_FPU_RESERVED | _FE_DIVBYZERO | _FE_OVERFLOW | _FE_INVALID) <<7); _FPU_SETMXCSR (mode_sse) ; return 1 ; }
int gsl_ieee_set_mode (int precision, int rounding, int exception_mask) { fpu_control_t mode, mode_sse; _FPU_GETCW (mode) ; mode &= _FPU_RESERVED ; switch (precision) { case GSL_IEEE_SINGLE_PRECISION: mode |= _FPU_SINGLE ; break ; case GSL_IEEE_DOUBLE_PRECISION: mode |= _FPU_DOUBLE ; break ; case GSL_IEEE_EXTENDED_PRECISION: mode |= _FPU_EXTENDED ; break ; default: mode |= _FPU_EXTENDED ; } switch (rounding) { case GSL_IEEE_ROUND_TO_NEAREST: mode |= _FPU_RC_NEAREST ; break ; case GSL_IEEE_ROUND_DOWN: mode |= _FPU_RC_DOWN ; break ; case GSL_IEEE_ROUND_UP: mode |= _FPU_RC_UP ; break ; case GSL_IEEE_ROUND_TO_ZERO: mode |= _FPU_RC_ZERO ; break ; default: mode |= _FPU_RC_NEAREST ; } if (exception_mask & GSL_IEEE_MASK_INVALID) mode |= _FPU_MASK_IM ; if (exception_mask & GSL_IEEE_MASK_DENORMALIZED) mode |= _FPU_MASK_DM ; if (exception_mask & GSL_IEEE_MASK_DIVISION_BY_ZERO) mode |= _FPU_MASK_ZM ; if (exception_mask & GSL_IEEE_MASK_OVERFLOW) mode |= _FPU_MASK_OM ; if (exception_mask & GSL_IEEE_MASK_UNDERFLOW) mode |= _FPU_MASK_UM ; if (exception_mask & GSL_IEEE_TRAP_INEXACT) { mode &= ~ _FPU_MASK_PM ; } else { mode |= _FPU_MASK_PM ; } _FPU_SETCW (mode) ; _FPU_GETMXCSR (mode_sse) ; mode_sse &= 0xFFFF0000 ; if (exception_mask & GSL_IEEE_MASK_INVALID) mode_sse |= _FPU_MASK_IM << 7 ; if (exception_mask & GSL_IEEE_MASK_DENORMALIZED) mode_sse |= _FPU_MASK_DM << 7 ; if (exception_mask & GSL_IEEE_MASK_DIVISION_BY_ZERO) mode_sse |= _FPU_MASK_ZM << 7 ; if (exception_mask & GSL_IEEE_MASK_OVERFLOW) mode_sse |= _FPU_MASK_OM << 7 ; if (exception_mask & GSL_IEEE_MASK_UNDERFLOW) mode_sse |= _FPU_MASK_UM << 7 ; if (exception_mask & GSL_IEEE_TRAP_INEXACT) { mode_sse &= ~ _FPU_MASK_PM << 7 ; } else { mode_sse |= _FPU_MASK_PM << 7 ; } _FPU_SETMXCSR (mode_sse) ; return GSL_SUCCESS ; }