int pthread_spin_unlock( pthread_spinlock_t *lock )
{
POSIX_Spinlock_Control *the_spinlock;
ISR_Level level;
the_spinlock = _POSIX_Spinlock_Get( lock );
level = the_spinlock->interrupt_state;
#if defined(POSIX_SPINLOCKS_ARE_SELF_CONTAINED)
#if defined(RTEMS_SMP)
_SMP_ticket_lock_Release(
&the_spinlock->Lock,
&_Per_CPU_Get()->Lock_stats_context
);
#endif
_ISR_Local_enable( level );
#else
if ( --_POSIX_Spinlock_Nest_level == 0 ) {
#if defined(RTEMS_SMP)
_POSIX_Spinlock_Owner = 0xffffffff;
_SMP_ticket_lock_Release(
&the_spinlock->Lock,
&_Per_CPU_Get()->Lock_stats_context
);
#endif
_ISR_Local_enable( level );
}
#endif
return 0;
}
void __ISR_Handler( uint32_t vector)
{
ISR_Level level;
_ISR_Local_disable( level );
_Thread_Dispatch_disable();
#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
if ( _ISR_Nest_level == 0 )
{
/* Install irq stack */
_old_stack_ptr = stack_ptr;
stack_ptr = _CPU_Interrupt_stack_high;
}
#endif
_ISR_Nest_level++;
_ISR_Local_enable( level );
/* call isp */
if ( _ISR_Vector_table[ vector])
(*_ISR_Vector_table[ vector ])( vector );
_ISR_Local_disable( level );
_Thread_Dispatch_enable( _Per_CPU_Get() );
_ISR_Nest_level--;
#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
if ( _ISR_Nest_level == 0 )
/* restore old stack pointer */
stack_ptr = _old_stack_ptr;
#endif
_ISR_Local_enable( level );
if ( _ISR_Nest_level )
return;
if ( !_Thread_Dispatch_is_enabled() ) {
return;
}
if ( _Thread_Dispatch_necessary ) {
_Thread_Dispatch();
}
}
void _Libatomic_Protect_end( void *ptr, __uint32_t isr_level )
{
(void) ptr;
#if defined(RTEMS_SMP)
_Atomic_Flag_clear( &_Libatomic_The_one_lock, ATOMIC_ORDER_SEQ_CST );
#endif
_ISR_Local_enable( isr_level );
}
static void _Mutex_Queue_release(
Mutex_Control *mutex,
ISR_Level level,
Thread_queue_Context *queue_context
)
{
_Thread_queue_Queue_release_critical(
&mutex->Queue.Queue,
&queue_context->Lock_context.Lock_context
);
_ISR_Local_enable( level );
}
static void set_thread_executing( Thread_Control *thread )
{
#if defined( PREVENT_SMP_ASSERT_FAILURES )
ISR_Level level;
_ISR_Local_disable( level );
#endif
_Thread_Executing = thread;
#if defined( PREVENT_SMP_ASSERT_FAILURES )
_ISR_Local_enable( level );
#endif
}
/*
* Send a command to the CPM RISC processer
*/
void *
M360AllocateBufferDescriptors (int count)
{
unsigned int i;
ISR_Level level;
void *bdp = NULL;
unsigned int want = count * sizeof(m360BufferDescriptor_t);
/*
* Running with interrupts disabled is usually considered bad
* form, but this routine is probably being run as part of an
* initialization sequence so the effect shouldn't be too severe.
*/
_ISR_Local_disable (level);
for (i = 0 ; i < sizeof(bdregions) / sizeof(bdregions[0]) ; i++) {
/*
* Verify that the region exists.
* This test is necessary since some chips have
* less dual-port RAM.
*/
if (bdregions[i].used == 0) {
volatile uint8_t *cp = bdregions[i].base;
*cp = 0xAA;
if (*cp != 0xAA) {
bdregions[i].used = bdregions[i].size;
continue;
}
*cp = 0x55;
if (*cp != 0x55) {
bdregions[i].used = bdregions[i].size;
continue;
}
*cp = 0x0;
}
if (bdregions[i].size - bdregions[i].used >= want) {
bdp = bdregions[i].base + bdregions[i].used;
bdregions[i].used += want;
break;
}
}
_ISR_Local_enable (level);
if (bdp == NULL)
rtems_panic ("Can't allocate %d buffer descriptor(s).\n", count);
return bdp;
}
static void set_thread_dispatch_necessary( bool dispatch_necessary )
{
#if defined( PREVENT_SMP_ASSERT_FAILURES )
ISR_Level level;
_ISR_Local_disable( level );
#endif
_Thread_Dispatch_necessary = dispatch_necessary;
if ( !dispatch_necessary ) {
_Thread_Heir = _Thread_Executing;
}
#if defined( PREVENT_SMP_ASSERT_FAILURES )
_ISR_Local_enable( level );
#endif
}
static void
_SMP_Multicasts_try_process( void )
{
unsigned long message;
Per_CPU_Control *cpu_self;
ISR_Level isr_level;
_ISR_Local_disable( isr_level );
cpu_self = _Per_CPU_Get();
message = _Atomic_Load_ulong( &cpu_self->message, ATOMIC_ORDER_RELAXED );
if ( message & SMP_MESSAGE_MULTICAST_ACTION ) {
if ( _Atomic_Compare_exchange_ulong( &cpu_self->message, &message,
message & ~SMP_MESSAGE_MULTICAST_ACTION, ATOMIC_ORDER_RELAXED,
ATOMIC_ORDER_RELAXED ) ) {
_SMP_Multicast_actions_process();
}
}
_ISR_Local_enable( isr_level );
}
void rtems_interrupt_enable(
rtems_interrupt_level previous_level
)
{
_ISR_Local_enable( previous_level );
}
