* The datasheet is wrong here, this doesn't have any * offset */ .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0), .common = { .reg = 0x008, .hw.init = CLK_HW_INIT("pll-audio-base", "hosc", &ccu_nm_ops, 0), }, }; static struct ccu_mult pll_video0_clk = { .enable = BIT(31), .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127), .frac = _SUNXI_CCU_FRAC(BIT(15), BIT(14), 270000000, 297000000), .common = { .reg = 0x010, .features = (CCU_FEATURE_FRACTIONAL | CCU_FEATURE_ALL_PREDIV), .prediv = 8, .hw.init = CLK_HW_INIT("pll-video0", "hosc", &ccu_mult_ops, 0), }, }; static struct ccu_nkmp pll_ve_clk = {
#define CCU_SUN9I_LOCK_REG 0x09c /* * The CPU PLLs are actually NP clocks, with P being /1 or /4. However * P should only be used for output frequencies lower than 228 MHz. * Neither mainline Linux, U-boot, nor the vendor BSPs use these. * * For now we can just model it as a multiplier clock, and force P to /1. */ #define SUN9I_A80_PLL_C0CPUX_REG 0x000 #define SUN9I_A80_PLL_C1CPUX_REG 0x004 static struct ccu_mult pll_c0cpux_clk = { .enable = BIT(31), .lock = BIT(0), .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .common = { .reg = SUN9I_A80_PLL_C0CPUX_REG, .lock_reg = CCU_SUN9I_LOCK_REG, .features = CCU_FEATURE_LOCK_REG, .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M", &ccu_mult_ops, CLK_SET_RATE_UNGATE), }, }; static struct ccu_mult pll_c1cpux_clk = { .enable = BIT(31), .lock = BIT(1), .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), .common = {