static void
awin_usb_phy_write(struct awinusb_softc *usbsc, u_int bit_addr, u_int bits,
u_int len)
{
bus_space_tag_t bst = usbsc->usbsc_bst;
bus_space_handle_t bsh = usbsc->usbsc_usb0_phy_csr_bsh;
uint32_t clk = AWIN_USB0_PHY_CTL_CLK0 << usbsc->usbsc_number;
uint32_t v = bus_space_read_4(bst, bsh, 0);
KASSERT((v & AWIN_USB0_PHY_CTL_CLK0) == 0);
KASSERT((v & AWIN_USB0_PHY_CTL_CLK1) == 0);
KASSERT((v & AWIN_USB0_PHY_CTL_CLK2) == 0);
v &= ~AWIN_USB0_PHY_CTL_ADDR;
v &= ~AWIN_USB0_PHY_CTL_DAT;
v |= __SHIFTIN(bit_addr, AWIN_USB0_PHY_CTL_ADDR);
/*
* Bitbang the data to the phy, bit by bit, incrementing bit address
* as we go.
*/
for (; len > 0; bit_addr++, bits >>= 1, len--) {
v |= __SHIFTIN(bits & 1, AWIN_USB0_PHY_CTL_DAT);
bus_space_write_4(bst, bsh, 0, v);
delay(1);
bus_space_write_4(bst, bsh, 0, v | clk);
delay(1);
bus_space_write_4(bst, bsh, 0, v);
delay(1);
v += __LOWEST_SET_BIT(AWIN_USB0_PHY_CTL_ADDR);
v &= ~AWIN_USB0_PHY_CTL_DAT;
}
}
static void
awin_hdmi_video_enable(struct awin_hdmi_softc *sc, bool enable)
{
uint32_t val;
val = HDMI_READ(sc, AWIN_HDMI_VID_CTRL_REG);
val &= ~AWIN_HDMI_VID_CTRL_SRC_SEL;
#ifdef AWIN_HDMI_CBGEN
val |= __SHIFTIN(AWIN_HDMI_VID_CTRL_SRC_SEL_CBGEN,
AWIN_HDMI_VID_CTRL_SRC_SEL);
#else
val |= __SHIFTIN(AWIN_HDMI_VID_CTRL_SRC_SEL_RGB,
AWIN_HDMI_VID_CTRL_SRC_SEL);
#endif
if (enable) {
val |= AWIN_HDMI_VID_CTRL_VIDEO_EN;
} else {
val &= ~AWIN_HDMI_VID_CTRL_VIDEO_EN;
}
HDMI_WRITE(sc, AWIN_HDMI_VID_CTRL_REG, val);
#if defined(AWIN_HDMI_DEBUG) && defined(DDB)
awin_hdmi_dump_regs();
#endif
}
static void
exynos_set_cpufreq(const struct cpu_freq *freqreq)
{
struct cpu_info *ci;
uint32_t regval;
int M, P, S;
int cii;
M = freqreq->M;
P = freqreq->P;
S = freqreq->S;
regval = __SHIFTIN(M, PLL_CON0_M) |
__SHIFTIN(P, PLL_CON0_P) |
__SHIFTIN(S, PLL_CON0_S);
/* enable PPL and write config */
regval |= PLL_CON0_ENABLE;
bus_space_write_4(&armv7_generic_bs_tag, exynos_cmu_apll_bsh, PLL_CON0_OFFSET,
regval);
/* update our cycle counter i.e. our CPU frequency for all CPUs */
for (CPU_INFO_FOREACH(cii, ci)) {
ci->ci_data.cpu_cc_freq = exynos_get_cpufreq();
}
}
static int
awin_p2wi_rsb_config(struct awin_p2wi_softc *sc, uint8_t rta, i2c_addr_t da,
int flags)
{
uint32_t dar, ctrl;
KASSERT(mutex_owned(&sc->sc_lock));
P2WI_WRITE(sc, AWIN_A31_P2WI_STAT_REG,
P2WI_READ(sc, AWIN_A31_P2WI_STAT_REG) & AWIN_A31_P2WI_STAT_MASK);
dar = __SHIFTIN(rta, AWIN_A80_RSB_DAR_RTA);
dar |= __SHIFTIN(da, AWIN_A80_RSB_DAR_DA);
P2WI_WRITE(sc, AWIN_A80_RSB_DAR_REG, dar);
P2WI_WRITE(sc, AWIN_A80_RSB_CMD_REG, AWIN_A80_RSB_CMD_IDX_SRTA);
/* Make sure the controller is idle */
ctrl = P2WI_READ(sc, AWIN_A31_P2WI_CTRL_REG);
if (ctrl & AWIN_A31_P2WI_CTRL_START_TRANS) {
device_printf(sc->sc_dev, "device is busy\n");
return EBUSY;
}
/* Start the transfer */
P2WI_WRITE(sc, AWIN_A31_P2WI_CTRL_REG,
ctrl | AWIN_A31_P2WI_CTRL_START_TRANS);
return awin_p2wi_wait(sc, flags);
}
void
tegra_mpio_pinmux_set_config(u_int reg, int flags, const char *func)
{
struct tegra_mpio_softc * const sc = tegra_mpio_lookup_softc();
const struct tegra_mpio_pinmux *pm;
uint32_t val;
int funcno, n;
pm = tegra_mpio_lookup_pinmux(reg);
KASSERT(pm != NULL);
for (n = 0, funcno = -1; n < __arraycount(pm->pm_func); n++) {
if (strcmp(pm->pm_func[n], func) == 0) {
funcno = n;
break;
}
}
KASSERT(funcno != -1);
val = MPIO_READ(sc, reg);
if (flags & GPIO_PIN_INPUT) {
val |= PINMUX_AUX_E_INPUT;
} else if (flags & GPIO_PIN_OUTPUT) {
val &= ~PINMUX_AUX_E_INPUT;
}
if (flags & GPIO_PIN_TRISTATE) {
val |= PINMUX_AUX_TRISTATE;
} else {
val &= ~PINMUX_AUX_TRISTATE;
}
val &= ~PINMUX_AUX_PUPD;
if (flags & GPIO_PIN_PULLUP) {
val |= __SHIFTIN(PINMUX_AUX_PUPD_PULL_UP,
PINMUX_AUX_PUPD);
} else if (flags & GPIO_PIN_PULLDOWN) {
val |= __SHIFTIN(PINMUX_AUX_PUPD_PULL_DOWN,
PINMUX_AUX_PUPD);
} else {
val |= __SHIFTIN(PINMUX_AUX_PUPD_NORMAL,
PINMUX_AUX_PUPD);
}
if (flags & GPIO_PIN_OPENDRAIN) {
val |= PINMUX_AUX_OD;
} else {
val &= ~PINMUX_AUX_OD;
}
val &= ~PINMUX_AUX_PM;
val |= __SHIFTIN(funcno, PINMUX_AUX_PM);
MPIO_WRITE(sc, reg, val);
}
void *
pci_msi_establish(struct pci_attach_args *pa, int level,
int (*func)(void *), void *arg)
{
int co;
struct intrhand *ih;
struct msi_hdl *msih;
struct cpu_info *ci;
struct intrsource *is;
pcireg_t reg;
if (!pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_MSI, &co, 0))
return NULL;
ih = intr_establish(-1, &msi_pic, -1, IST_EDGE, level, func, arg, 0);
if (ih == NULL)
return NULL;
msih = malloc(sizeof(*msih), M_DEVBUF, M_WAITOK);
msih->ih = ih;
msih->pc = pa->pa_pc;
msih->tag = pa->pa_tag;
msih->co = co;
ci = ih->ih_cpu;
is = ci->ci_isources[ih->ih_slot];
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, co + PCI_MSI_CTL);
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MADDR64_LO,
LAPIC_MSIADDR_BASE |
__SHIFTIN(ci->ci_cpuid, LAPIC_MSIADDR_DSTID_MASK));
if (reg & PCI_MSI_CTL_64BIT_ADDR) {
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MADDR64_HI,
0);
/* XXX according to the manual, ASSERT is unnecessary if
* EDGE
*/
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MDATA64,
__SHIFTIN(is->is_idtvec, LAPIC_MSIDATA_VECTOR_MASK) |
LAPIC_MSIDATA_TRGMODE_EDGE | LAPIC_MSIDATA_LEVEL_ASSERT |
LAPIC_MSIDATA_DM_FIXED);
} else {
/* XXX according to the manual, ASSERT is unnecessary if
* EDGE
*/
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_MDATA,
__SHIFTIN(is->is_idtvec, LAPIC_MSIDATA_VECTOR_MASK) |
LAPIC_MSIDATA_TRGMODE_EDGE | LAPIC_MSIDATA_LEVEL_ASSERT |
LAPIC_MSIDATA_DM_FIXED);
}
pci_conf_write(pa->pa_pc, pa->pa_tag, co + PCI_MSI_CTL,
PCI_MSI_CTL_MSI_ENABLE);
return msih;
}
/*
* The fegetenv() function shall attempt to store the current floating-point
* environment in the object pointed to by envp.
*/
int
fegetenv(fenv_t *envp)
{
#ifdef __SOFTFP__
*envp = __SHIFTIN(fpgetround(), VFP_FPSCR_RMODE)
| __SHIFTIN(fpgetmask(), VFP_FPSCR_ESUM)
| __SHIFTIN(fpgetsticky(), VFP_FPSCR_CSUM);
#else
*envp = armreg_fpscr_read();
#endif
return 0;
}
static int
rtw_sa2400_agc_init(struct rtw_sa2400 *sa)
{
uint32_t agc;
agc = __SHIFTIN(25, SA2400_AGC_MAXGAIN_MASK);
agc |= __SHIFTIN(7, SA2400_AGC_BBPDELAY_MASK);
agc |= __SHIFTIN(15, SA2400_AGC_LNADELAY_MASK);
agc |= __SHIFTIN(27, SA2400_AGC_RXONDELAY_MASK);
return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_AGC,
agc);
}
static void
acpicpu_md_pstate_fidvid_write(uint32_t fid,
uint32_t vid, uint32_t cnt, uint32_t tmo)
{
uint64_t val = 0;
val |= __SHIFTIN(fid, MSR_0FH_CONTROL_FID);
val |= __SHIFTIN(vid, MSR_0FH_CONTROL_VID);
val |= __SHIFTIN(cnt, MSR_0FH_CONTROL_CNT);
val |= __SHIFTIN(0x1, MSR_0FH_CONTROL_CHG);
wrmsr(MSR_0FH_CONTROL, val);
DELAY(tmo);
}
void
imxusb_ulpi_write(struct imxehci_softc *sc, int addr, uint8_t data)
{
uint32_t reg;
ulpi_wakeup(sc, TIMEOUT);
reg = ULPI_RUN | ULPI_RW | __SHIFTIN(addr, ULPI_ADDR) | __SHIFTIN(data, ULPI_DATWR);
bus_space_write_4(sc->sc_iot, sc->sc_ioh, IMXUSB_ULPIVIEW, reg);
ulpi_wait(sc, TIMEOUT);
return;
}
/*
* The feholdexcept() function shall save the current floating-point
* environment in the object pointed to by envp, clear the floating-point
* status flags, and then install a non-stop (continue on floating-point
* exceptions) mode, if available, for all floating-point exceptions.
*/
int
feholdexcept(fenv_t *envp)
{
#ifdef __SOFTFP__
*envp = __SHIFTIN(fpgetround(), VFP_FPSCR_RMODE)
| __SHIFTIN(fpgetmask(), VFP_FPSCR_ESUM)
| __SHIFTIN(fpgetsticky(), VFP_FPSCR_CSUM);
fpsetmask(0);
fpsetsticky(0);
#else
*envp = armreg_fpscr_read();
armreg_fpscr_write((*envp) & ~(VFP_FPSCR_ESUM|VFP_FPSCR_CSUM));
#endif
return 0;
}
static int
awin_hdmi_i2c_xfer_1_3(void *priv, i2c_addr_t addr, uint8_t block, uint8_t reg,
size_t len, int type, int flags)
{
struct awin_hdmi_softc *sc = priv;
uint32_t val;
int retry;
val = HDMI_READ(sc, AWIN_HDMI_DDC_CTRL_REG);
val &= ~AWIN_HDMI_DDC_CTRL_FIFO_DIR;
HDMI_WRITE(sc, AWIN_HDMI_DDC_CTRL_REG, val);
val |= __SHIFTIN(block, AWIN_HDMI_DDC_SLAVE_ADDR_0);
val |= __SHIFTIN(0x60, AWIN_HDMI_DDC_SLAVE_ADDR_1);
val |= __SHIFTIN(reg, AWIN_HDMI_DDC_SLAVE_ADDR_2);
val |= __SHIFTIN(addr, AWIN_HDMI_DDC_SLAVE_ADDR_3);
HDMI_WRITE(sc, AWIN_HDMI_DDC_SLAVE_ADDR_REG, val);
val = HDMI_READ(sc, AWIN_HDMI_DDC_FIFO_CTRL_REG);
val |= AWIN_HDMI_DDC_FIFO_CTRL_ADDR_CLEAR;
HDMI_WRITE(sc, AWIN_HDMI_DDC_FIFO_CTRL_REG, val);
HDMI_WRITE(sc, AWIN_HDMI_DDC_BYTE_COUNTER_REG, len);
HDMI_WRITE(sc, AWIN_HDMI_DDC_COMMAND_REG, type);
val = HDMI_READ(sc, AWIN_HDMI_DDC_CTRL_REG);
val |= AWIN_HDMI_DDC_CTRL_ACCESS_CMD_START;
HDMI_WRITE(sc, AWIN_HDMI_DDC_CTRL_REG, val);
retry = 1000;
while (--retry > 0) {
val = HDMI_READ(sc, AWIN_HDMI_DDC_CTRL_REG);
if ((val & AWIN_HDMI_DDC_CTRL_ACCESS_CMD_START) == 0)
break;
delay(1000);
}
if (retry == 0)
return ETIMEDOUT;
val = HDMI_READ(sc, AWIN_HDMI_DDC_INT_STATUS_REG);
if ((val & AWIN_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE) == 0) {
device_printf(sc->sc_dev, "xfer failed, status=%08x\n", val);
return EIO;
}
return 0;
}
void
db_show_tlb_cmd(db_expr_t addr, bool have_addr, db_expr_t count, const char *modif)
{
const struct db_tlbinfo * const dti = tlb_lookup_tlbinfo();
if (have_addr) {
const vaddr_t vpn = (vaddr_t)addr >> L2_S_SHIFT;
const u_int va_index = vpn & dti->dti_index;
for (size_t way = 0; way < 2; way++) {
armreg_tlbdataop_write(
__SHIFTIN(va_index, dti->dti_index)
| __SHIFTIN(way, ARM_TLBDATAOP_WAY));
__asm("isb");
const uint32_t d0 = armreg_tlbdata0_read();
const uint32_t d1 = armreg_tlbdata1_read();
if ((d0 & ARM_TLBDATA_VALID)
&& vpn == (*dti->dti_decode_vpn)(va_index, d0, d1)) {
(*dti->dti_print_header)();
(*dti->dti_print_entry)(way, va_index, d0, d1);
return;
}
}
db_printf("VA %#"DDB_EXPR_FMT"x not found in TLB\n", addr);
return;
}
bool first = true;
size_t n = 0;
for (size_t va_index = 0; va_index <= dti->dti_index; va_index++) {
for (size_t way = 0; way < 2; way++) {
armreg_tlbdataop_write(
__SHIFTIN(way, ARM_TLBDATAOP_WAY)
| __SHIFTIN(va_index, dti->dti_index));
__asm("isb");
const uint32_t d0 = armreg_tlbdata0_read();
const uint32_t d1 = armreg_tlbdata1_read();
if (d0 & ARM_TLBDATA_VALID) {
if (first) {
(*dti->dti_print_header)();
first = false;
}
(*dti->dti_print_entry)(way, va_index, d0, d1);
n++;
}
}
}
db_printf("%zu TLB valid entries found\n", n);
}
int
feenableexcept(int excepts)
{
const uint32_t __fpcr = reg_fpcr_read();
reg_fpcr_write((__fpcr & ~FPCR_ESUM) | __SHIFTIN(excepts, FPCR_ESUM));
return __SHIFTOUT(__fpcr, FPCR_ESUM);
}
/*
* The feraiseexcept() function shall attempt to raise the supported
* floating-point exceptions represented by the argument excepts. The order
* in which these floating-point exceptions are raised is unspecified.
*/
int
feraiseexcept(int excepts)
{
#ifndef lint
_DIAGASSERT((except & ~FE_ALL_EXCEPT) == 0);
#endif
#ifdef __SOFTFP__
excepts &= fpgetsticky();
if (excepts) {
siginfo_t info;
memset(&info, 0, sizeof info);
info.si_signo = SIGFPE;
info.si_pid = getpid();
info.si_uid = geteuid();
if (excepts & FE_UNDERFLOW)
info.si_code = FPE_FLTUND;
else if (excepts & FE_OVERFLOW)
info.si_code = FPE_FLTOVF;
else if (excepts & FE_DIVBYZERO)
info.si_code = FPE_FLTDIV;
else if (excepts & FE_INVALID)
info.si_code = FPE_FLTINV;
else if (excepts & FE_INEXACT)
info.si_code = FPE_FLTRES;
sigqueueinfo(getpid(), &info);
}
#else
int fpscr = armreg_fpscr_read();
fpscr = (fpscr & ~VFP_FPSCR_ESUM) | __SHIFTIN(excepts, VFP_FPSCR_ESUM);
armreg_fpscr_write(fpscr);
#endif
return 0;
}
static void
bcmmdio_ccb_attach(device_t parent, device_t self, void *aux)
{
struct bcmmdio_softc * const sc = device_private(self);
struct bcmccb_attach_args * const ccbaa = aux;
const struct bcm_locators * const loc = &ccbaa->ccbaa_loc;
sc->sc_dev = self;
sc->sc_bst = ccbaa->ccbaa_ccb_bst;
sc->sc_lock = mutex_obj_alloc(MUTEX_DEFAULT, IPL_VM);
bus_space_subregion(sc->sc_bst, ccbaa->ccbaa_ccb_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_bsh);
uint32_t miimgt = bcmmdio_read_4(sc, MIIMGT);
uint32_t div = __SHIFTOUT(miimgt, MIIMGT_MDCDIV);
if (div == 0) {
div = 33; // divisor to get 2MHz
miimgt &= ~MIIMGT_MDCDIV;
miimgt |= __SHIFTIN(div, MIIMGT_MDCDIV);
bcmmdio_write_4(sc, MIIMGT, miimgt);
}
uint32_t freq = 66000000 / div;
aprint_naive("\n");
aprint_normal(": MDIO bus @ %u MHz\n", freq / 1000000);
}
static int
dtrace_trapper(u_int addr, struct trapframe *frame)
{
int op;
struct trapframe back;
u_int insn = read_insn(addr, false);
if (dtrace_invop_jump_addr == NULL || dtrace_emulation_jump_addr == NULL)
return 1;
if (!DTRACE_IS_BREAKPOINT(insn))
return 1;
/* cond value is encoded in the first byte */
if (!arm_cond_ok_p(__SHIFTIN(insn, INSN_COND_MASK), frame->tf_spsr)) {
frame->tf_pc += INSN_SIZE;
return 0;
}
back = *frame;
op = dtrace_invop_jump_addr(addr, (uintptr_t *) frame->tf_svc_sp, frame->tf_r0);
*frame = back;
dtrace_emulation_jump_addr(op, frame);
return 0;
}
static int
rtw_bbp_init(struct rtw_regs *regs, struct rtw_bbpset *bb, int antdiv,
int dflantb, uint8_t cs_threshold, u_int freq)
{
int rc;
uint32_t sys2, sys3;
sys2 = bb->bb_sys2;
if (antdiv)
sys2 |= RTW_BBP_SYS2_ANTDIV;
sys3 = bb->bb_sys3 |
__SHIFTIN(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK);
#define RTW_BBP_WRITE_OR_RETURN(reg, val) \
if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \
return rc;
RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS1, bb->bb_sys1);
RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TXAGC, bb->bb_txagc);
RTW_BBP_WRITE_OR_RETURN(RTW_BBP_LNADET, bb->bb_lnadet);
RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCINI, bb->bb_ifagcini);
RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCLIMIT, bb->bb_ifagclimit);
RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCDET, bb->bb_ifagcdet);
if ((rc = rtw_bbp_preinit(regs, bb->bb_antatten, dflantb, freq)) != 0)
return rc;
RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TRL, bb->bb_trl);
RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS2, sys2);
RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS3, sys3);
RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHESTLIM, bb->bb_chestlim);
RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHSQLIM, bb->bb_chsqlim);
return 0;
}
void
prcm_mpu_pll_config(u_int mpupll_m)
{
uint32_t clkmode = prcm_read_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_CLKMODE_DPLL_MPU);
uint32_t clksel = prcm_read_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_CLKSEL_DPLL_MPU);
//uint32_t div_m2 = prcm_read_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_DIV_M2_DPLL_MPU);
/* Request the DPLL be put into bypass mode */
prcm_write_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_CLKMODE_DPLL_MPU, AM335X_PRCM_CM_CLKMODE_DPLL_MN_BYP_MODE);
/* Wait for it to go into bypass */
while (prcm_read_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_IDLEST_DPLL_MPU) != AM335X_PRCM_CM_IDLEST_DPLL_ST_DPLL_CLK_MN_BYPASS) {
/* nothing */
}
/* Replace multipler */
clksel &= ~AM335X_PRCM_CM_CLKSEL_DPLL_MULT;
clksel |= __SHIFTIN(mpupll_m, AM335X_PRCM_CM_CLKSEL_DPLL_MULT);
prcm_write_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_CLKSEL_DPLL_MPU, clksel);
/* Exit bypass mode */
clkmode |= AM335X_PRCM_CM_CLKMODE_DPLL_LOCK_MODE;
prcm_write_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_CLKMODE_DPLL_MPU, clkmode);
/* Wait for the DPLL to lock */
while (prcm_read_4(AM335X_PRCM_CM_WKUP, AM335X_PRCM_CM_IDLEST_DPLL_MPU) != AM335X_PRCM_CM_IDLEST_DPLL_ST_DPLL_CLK_LOCKED) {
/* nothing */
}
}
static int
awin_hdmi_i2c_reset(struct awin_hdmi_softc *sc, int flags)
{
uint32_t hpd, ctrl;
hpd = HDMI_READ(sc, AWIN_HDMI_HPD_REG);
if ((hpd & AWIN_HDMI_HPD_HOTPLUG_DET) == 0) {
device_printf(sc->sc_dev, "no device detected\n");
return ENODEV; /* no device plugged in */
}
if (HDMI_1_3_P(sc)) {
HDMI_WRITE(sc, AWIN_HDMI_DDC_FIFO_CTRL_REG, 0);
HDMI_WRITE(sc, AWIN_HDMI_DDC_CTRL_REG,
AWIN_HDMI_DDC_CTRL_EN | AWIN_HDMI_DDC_CTRL_SW_RST);
delay(1000);
ctrl = HDMI_READ(sc, AWIN_HDMI_DDC_CTRL_REG);
if (ctrl & AWIN_HDMI_DDC_CTRL_SW_RST) {
device_printf(sc->sc_dev, "reset failed (1.3)\n");
return EBUSY;
}
/* N=5,M=1 */
HDMI_WRITE(sc, AWIN_HDMI_DDC_CLOCK_REG,
__SHIFTIN(5, AWIN_HDMI_DDC_CLOCK_N) |
__SHIFTIN(1, AWIN_HDMI_DDC_CLOCK_M));
HDMI_WRITE(sc, AWIN_HDMI_DDC_DBG_REG, 0x300);
} else {
HDMI_WRITE(sc, AWIN_A31_HDMI_DDC_CTRL_REG,
AWIN_A31_HDMI_DDC_CTRL_SW_RST);
/* N=1,M=12 */
HDMI_WRITE(sc, AWIN_A31_HDMI_DDC_CLOCK_REG,
__SHIFTIN(1, AWIN_HDMI_DDC_CLOCK_N) |
__SHIFTIN(12, AWIN_HDMI_DDC_CLOCK_M));
HDMI_WRITE(sc, AWIN_A31_HDMI_DDC_CTRL_REG,
AWIN_A31_HDMI_DDC_CTRL_SDA_PAD_EN |
AWIN_A31_HDMI_DDC_CTRL_SCL_PAD_EN |
AWIN_A31_HDMI_DDC_CTRL_EN);
}
return 0;
}
static void
awin_otg_attach(device_t parent, device_t self, void *aux)
{
struct awin_otg_softc *sc = device_private(self);
struct awinio_attach_args * const aio = aux;
const struct awin_locators * const loc = &aio->aio_loc;
aprint_naive("\n");
aprint_normal(": OTG\n");
if (awin_chip_id() == AWIN_CHIP_ID_A31) {
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_USB_CLK_REG,
AWIN_A31_USB_CLK_USBPHY0_ENABLE |
AWIN_A31_USB_CLK_PHY0_ENABLE, 0);
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_AHB_GATING0_REG, AWIN_A31_AHB_GATING0_USB0, 0);
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_A31_AHB_RESET0_REG, AWIN_A31_AHB_RESET0_USBOTG_RST, 0);
} else {
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_AHB_GATING0_REG, AWIN_AHB_GATING0_USB0, 0);
awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
AWIN_USB_CLK_REG,
AWIN_USB_CLK_USBPHY_ENABLE|AWIN_USB_CLK_PHY0_ENABLE, 0);
awin_reg_set_clear(aio->aio_core_bst, aio->aio_core_bsh,
AWIN_SRAM_OFFSET + AWIN_SRAM_CTL1_REG,
__SHIFTIN(AWIN_SRAM_CTL1_SRAMD_MAP_USB0,
AWIN_SRAM_CTL1_SRAMD_MAP),
0);
}
sc->sc_motg.sc_dev = self;
sc->sc_motg.sc_bus.dmatag = aio->aio_dmat;
sc->sc_motg.sc_iot = aio->aio_core_bst;
bus_space_subregion(sc->sc_motg.sc_iot, aio->aio_core_bsh,
loc->loc_offset, loc->loc_size, &sc->sc_motg.sc_ioh);
sc->sc_motg.sc_size = loc->loc_size;
sc->sc_motg.sc_intr_poll = awin_otg_poll;
sc->sc_motg.sc_intr_poll_arg = sc;
sc->sc_motg.sc_mode = MOTG_MODE_HOST;
sc->sc_motg.sc_ep_max = 5;
sc->sc_motg.sc_ep_fifosize = 512;
sc->sc_ih = intr_establish(loc->loc_intr, IPL_USB, IST_LEVEL,
awin_otg_intr, sc);
if (sc->sc_ih == NULL) {
aprint_error_dev(self, "couldn't establish interrupt %d\n",
loc->loc_intr);
return;
}
device_printf(self, "interrupting at irq %d\n", loc->loc_intr);
awin_otg_init(sc);
motg_init(&sc->sc_motg);
}
fp_except
fpsetmask(fp_except mask)
{
#if 0
return __SHIFTOUT(riscvreg_fcsr_write_fmask(__SHIFTIN(mask, FCSR_MASK)), FCSR_FMASK);
#else
return 0;
#endif
}
fp_except_t
fpsetsticky(fp_except_t sticky)
{
const uint32_t old_fpsr = reg_fpsr_read();
const uint32_t new_fpsr = (old_fpsr & ~FPSR_CSUM)
| __SHIFTIN(sticky, FPSR_CSUM);
reg_fpsr_write(new_fpsr);
return __SHIFTOUT(old_fpsr, FPSR_CSUM);
}
void
bwi_phy_set_bbp_atten(struct bwi_mac *mac, uint16_t bbp_atten)
{
struct bwi_phy *phy = &mac->mac_phy;
uint16_t mask = __BITS(3, 0);
if (phy->phy_version == 0) {
CSR_FILT_SETBITS_2(mac->mac_sc, BWI_BBP_ATTEN, ~mask,
__SHIFTIN(bbp_atten, mask));
} else {
if (phy->phy_version > 1)
mask <<= 2;
else
mask <<= 3;
PHY_FILT_SETBITS(mac, BWI_PHYR_BBP_ATTEN, ~mask,
__SHIFTIN(bbp_atten, mask));
}
}
void
bcm_pwm_dma_enable(struct bcm_pwm_channel *pwm, bool enable)
{
struct bcm2835pwm_softc *sc = pwm->sc;
uint32_t w;
#if 0
w = PWM_READ(sc, PWM_DMAC);
if (enable)
w |= PWM_DMAC_ENAB;
else
w &= ~PWM_DMAC_ENAB;
#else
w = (enable ? PWM_DMAC_ENAB : 0)
| __SHIFTIN(7, PWM_DMAC_PANIC)
| __SHIFTIN(7, PWM_DMAC_DREQ);
#endif
PWM_WRITE(sc, PWM_DMAC, w & ~PWM_DMAC_WRITEZERO);
}
static int
rtw_max2820_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower,
enum rtw_pwrstate power)
{
struct rtw_max2820 *mx = (struct rtw_max2820 *)rf;
struct rtw_rfbus *bus = &mx->mx_bus;
int rc;
if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TEST,
MAX2820_TEST_DEFAULT)) != 0)
return rc;
if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE,
MAX2820_ENABLE_DEFAULT)) != 0)
return rc;
/* skip configuration if it's time to sleep or to power-down. */
if ((rc = rtw_max2820_pwrstate(rf, power)) != 0)
return rc;
else if (power == RTW_OFF || power == RTW_SLEEP)
return 0;
if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_SYNTH,
MAX2820_SYNTH_R_44MHZ)) != 0)
return rc;
if ((rc = rtw_max2820_tune(rf, freq)) != 0)
return rc;
/* XXX The MAX2820 datasheet indicates that 1C and 2C should not
* be changed from 7, however, the reference driver sets them
* to 4 and 1, respectively.
*/
if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_RECEIVE,
MAX2820_RECEIVE_DL_DEFAULT |
__SHIFTIN(4, MAX2820A_RECEIVE_1C_MASK) |
__SHIFTIN(1, MAX2820A_RECEIVE_2C_MASK))) != 0)
return rc;
return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TRANSMIT,
MAX2820_TRANSMIT_PA_DEFAULT);
}
static pci_intr_handle_t
pci_msi_calculate_handle(struct pic *msi_pic, int vector)
{
pci_intr_handle_t pih;
KASSERT(msipic_is_msi_pic(msi_pic));
pih = __SHIFTIN((uint64_t)msipic_get_devid(msi_pic), MSI_INT_DEV_MASK)
| __SHIFTIN((uint64_t)vector, MSI_INT_VEC_MASK)
| APIC_INT_VIA_MSI;
if (msi_pic->pic_type == PIC_MSI)
MSI_INT_MAKE_MSI(pih);
else if (msi_pic->pic_type == PIC_MSIX)
MSI_INT_MAKE_MSIX(pih);
else
panic("%s: Unexpected pic_type: %d\n", __func__,
msi_pic->pic_type);
return pih;
}
/*
* The fesetround() function shall establish the rounding direction represented
* by its argument round. If the argument is not equal to the value of a
* rounding direction macro, the rounding direction is not changed.
*/
int
fesetround(int round)
{
#ifndef lint
_DIAGASSERT(!(round & ~__SHIFTOUT(FPCR_RMODE, FPCR_RMODE)));
#endif
unsigned int fpcr = reg_fpcr_read() & ~FPCR_RMODE;
fpcr |= __SHIFTIN(round, FPCR_RMODE);
reg_fpcr_write(fpcr);
return 0;
}
/*
* The fesetenv() function shall attempt to establish the floating-point
* environment represented by the object pointed to by envp. The fesetenv()
* function does not raise floating-point exceptions, but only installs the
* state of the floating-point status flags represented through its argument.
*/
int
fesetenv(const fenv_t *envp)
{
#ifdef __SOFTFP__
(void)fpsetround(__SHIFTIN(*envp, VFP_FPSCR_RMODE));
(void)fpsetmask(__SHIFTOUT(*envp, VFP_FPSCR_ESUM));
(void)fpsetsticky(__SHIFTOUT(*envp, VFP_FPSCR_CSUM));
#else
armreg_fpscr_write(*envp);
#endif
return 0;
}
/*
* The fesetexceptflag() function shall attempt to set the floating-point
* status flags indicated by the argument excepts to the states stored in the
* object pointed to by flagp. The value pointed to by flagp shall have been
* set by a previous call to fegetexceptflag() whose second argument
* represented at least those floating-point exceptions represented by the
* argument excepts. This function does not raise floating-point exceptions,
* but only sets the state of the flags.
*/
int
fesetexceptflag(const fexcept_t *flagp, int excepts)
{
#ifndef lint
_DIAGASSERT((except & ~FE_ALL_EXCEPT) == 0);
#endif
unsigned int fpsr = reg_fpsr_read();
fpsr &= ~__SHIFTIN(excepts, FPSR_CSUM);
fpsr |= __SHIFTIN((*flagp & excepts), FPSR_CSUM);
reg_fpsr_write(fpsr);
return 0;
}
