void cfgSystemClock( void ) { // set up internal clock UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation UCSCTL2 = 0x0300; // Set DCO Multiplier for 30MHz __bic_SR_register(SCG0); // re-enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle __delay_cycles(375000); // Loop until XT1 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag }
/* * main.c */ int main(void) { WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer P8SEL |= BIT5 | BIT6; //I2C Pins P8.5; P8.6 UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2 | SELS_4 | SELM_4; // Set ACLK = REFO; SMCLK;MLCK = DCODIV __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_3; // Select DCO range 10MHz operation UCSCTL2 = FLLD_0 + 151; // Set DCO Multiplier for 5MHz //UCSCTL2 = FLLD_0 + 243; // Set DCO Multiplier for 8MHz // (N + 1) * FLLRef = Fdco // (243 + 1) * 32768 = 8MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop// Clock setup // Enable interrupts __bis_SR_register(GIE); // Configure USCI_B0 for I2 mode - Sending UCB1CTL1 |= UCSWRST; // Software reset enabled UCB1CTL0 |= UCMODE_3 | UCMST | UCSYNC; // I2C mode, master, sync UCB1BRW = 100; // Baudrate = SMCLK / 100; UCB1CTL1 |= UCSSEL_2 | UCTR; // SMCLK, TX UCB1I2CSA = MLX90615_I2C_ADDRESS; // I2C Address UCB1CTL1 &= ~UCSWRST; // Clear reset for(;;){ // Send object temperature read command UCB1CTL1 |= UCTXSTT | UCTR; // Send start while(!(UCB1IFG & UCTXIFG)); // Wait for TX interrupt flag UCB1TXBUF = MLX90615_TOBJ1; // Send object temperature command while(!(UCB1IFG & UCTXIFG)); // Wait for TX interrupt flag UCB1CTL1 &= ~UCTR; // Change to receive UCB1CTL1 |= UCTXSTT; // Send restart while(UCB1CTL1 & UCTXSTT); // Wait for restart // Receive Bytes while(!(UCB1IFG & UCRXIFG)); // Wait for RX interrupt flag g_mlxValBytes[0] = UCB1RXBUF; // 0th byte while(!(UCB1IFG & UCRXIFG)); // Wait for RX interrupt flag g_mlxValBytes[1] = UCB1RXBUF; // 1st byte while(!(UCB1IFG & UCRXIFG)); // Wait for RX interrupt flag g_mlxValBytes[2] = UCB1RXBUF; // 2nd byte UCB1CTL1 |= UCTXSTP; // Send stop while(UCB1CTL1 & UCTXSTP); // Wait for stop g_mlxValBytes[2] = UCB1RXBUF; // 2nd byte // Calculate temperature g_objectTemp = 0.0; uint16_t tempVals = ( ((uint16_t) g_mlxValBytes[1]) << 8 ) | ( (uint16_t) g_mlxValBytes[0] ); g_objectTemp = ((float) tempVals) * 0.02 - 273.15; temps[counter] = g_objectTemp; //temps[counter] = g_objectTemp*100; counter = (counter+1)%100; } return 0; }
__interrupt void PORT2_ISR(void) { __bic_SR_register(GIE); UCA0TXBUF = 1; P2IFG &= ~BIT1; return ; }
void clock_config(){ // Increase Vcore setting to level2 to support fsystem=20MHz // NOTE: Change core voltage one level at a time.. SetVcoreUp (0x01); SetVcoreUp (0x02); UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_6; // Select DCO range 32MHz operation UCSCTL2 = FLLD_1 + 487; // Set DCO Multiplier for 16MHz // (N + 1) * FLLRef = Fdco // (487 + 1) * 32768 = 16MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 16 MHz / 32,768 Hz = 500000 = MCLK cycles for DCO to settle __delay_cycles(500000); // Loop until XT1,XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag }
/* * main.c */ void clockSetup(){ /* * Need to understand more about this...c * */ //P2DIR == 0x00; // for pulse generating P4DIR |= 0x80; // P4.7 SMCLK P4SEL |= 0x80; // P4.7 for debugging freq. P11DIR |= BIT0; // ACLK P11SEL |= BIT0; // P11.0 UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_4; // Set ACLK = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation UCSCTL2 = FLLD_1 + 122; //122 // Set DCO Multiplier for 8MHz UCSCTL5 = DIVA__4 + DIVS__4; // test 2MHz // (244 + 1) * 32768 = 8MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle }
uint8_t ucs_clockinit(unsigned long freq, uint8_t use_xt1, uint8_t vlo_as_aclk) { unsigned long attempts = 0; //, divided; uint16_t flld; static uint8_t did_vcoreup = 0; UCSCTL4 = SELM__DCOCLK | SELS__DCOCLK; if (vlo_as_aclk) UCSCTL4 = (UCSCTL4 & ~SELA_7) | SELA__VLOCLK; if (use_xt1) { PJSEL |= BIT4|BIT5; UCSCTL6 &= ~XT1OFF; UCSCTL6 = (UCSCTL6 & ~(XCAP_3|XT1DRIVE_3)) | XCAP_0 | XT1DRIVE_3; if (!vlo_as_aclk) UCSCTL4 = (UCSCTL4 & ~SELA_7) | SELA__XT1CLK; // Wait for XT1 to stabilize do { UCSCTL7 &= ~XT1LFOFFG; attempts++; } while (UCSCTL7 & XT1LFOFFG && attempts < 1000000); if (attempts == 1000000) return 0; // XT1 FAILED } else { UCSCTL6 |= XT1OFF; UCSCTL7 &= ~(XT1LFOFFG | XT1HFOFFG); UCSCTL3 = SELREF__REFOCLK; } // Using frequency, determine which VCore level we should achieve. // Set Vcore to maximum if (!did_vcoreup) { SetVCoreUp(1); SetVCoreUp(2); SetVCoreUp(3); did_vcoreup = 1; } // Initialize DCO __bis_SR_register(SCG0); // Disable FLL control loop UCSCTL0 = 0x0000; // Determine which DCORSEL we should use UCSCTL1 = _dcorsel_compute_f5172(freq); // FLL reference is 32768Hz, determine multiplier flld = _flld_compute(freq); UCSCTL2 = ((flld/2) << 12) | (uint16_t)(freq / 32768UL / flld); __bic_SR_register(SCG0); // Re-enable FLL control loop // Loop until XT1 & DCO fault flags have cleared do { UCSCTL7 &= ~(XT1LFOFFG | XT1HFOFFG | DCOFFG); SFRIFG1 &= ~OFIFG; } while ( (UCSCTL7 & DCOFFG) || (use_xt1 && (SFRIFG1 & OFIFG)) ); // DCOCLK stable return 1; }
// ACLK = REFO = 32kHz, MCLK = SMCLK = 25MHz // // MSP430F5529 // ----------------- // /|\| | // | | P1.0|-->ACLK // --|RST P7.7|-->MCLK // | P2.2|-->SMCLK void SET_FLL_25MHZ(void) { // Increase Vcore setting to level3 to support fsystem=25MHz // NOTE: Change core voltage one level at a time.. SetVcoreUp (0x01); SetVcoreUp (0x02); SetVcoreUp (0x03); UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_7; // Select DCO range 50MHz operation UCSCTL2 = FLLD_0 + 762; // Set DCO Multiplier for 25MHz // (N + 1) * FLLRef = Fdco // (762 + 1) * 32768 = 25MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 25 MHz / 32,768 Hz ~ 780k MCLK cycles for DCO to settle __delay_cycles(782000); // Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag }
// MSP430F552x Demo - Software Toggle P1.1 with 12MHz DCO // // Description: Toggle P1.1 by xor'ing P1.1 inside of a software loop. // ACLK is rought out on pin P1.0, SMCLK is brought out on P2.2, and MCLK // is brought out on pin P7.7. // ACLK = REFO = 32kHz, MCLK = SMCLK = 12MHz // // MSP430F552x // ----------------- // /|\| | // | | P1.0|-->ACLK // --|RST P7.7|-->MCLK // | P2.2|-->SMCLK void SET_FLL_12MHZ(void) { UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz // (N + 1) * FLLRef = Fdco // (374 + 1) * 32768 = 12MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle __delay_cycles(375000); // Loop until XT1,XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag }
// MSP430F552x Demo - Software Toggle P1.1 with 8MHz DCO // // Description: Toggle P1.1 by xor'ing P1.1 inside of a software loop. // ACLK is rought out on pin P1.0, SMCLK is brought out on P2.2, and MCLK // is brought out on pin P7.7. // ACLK = REFO = 32kHz, MCLK = SMCLK = 8MHz // // MSP430F5529 // ----------------- // /|\| | // | | P1.0|-->ACLK // --|RST P7.7|-->MCLK // | P2.2|-->SMCLK void SET_FLL_8MHZ(void) { UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx // Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation UCSCTL2 |= 249; // Set DCO Multiplier for 8MHz // (N + 1) * FLLRef = Fdco // (249 + 1) * 32768 = 8MHz __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle __delay_cycles(250000); }
void hardware_clock_init(void) { uint8_t i; __disable_interrupt(); // Disable global interrupts // Enable XT2 pins P5SEL |= 0x0C; // Use REFO as the FLL reference UCSCTL3 = (UCSCTL3 & ~(SELREF_7)) | (SELREF_2); UCSCTL4 |= SELA__REFOCLK; // ACLK source uint16_t srRegisterState = __read_status_register() & SCG0; __bis_SR_register(SCG0); // Set lowest possible DCOx, MODx UCSCTL0 = 0x0000; // Select DCO range 50MHz operation UCSCTL1 = DCORSEL_7 | 1; UCSCTL2 = FLLD_0 + 550; __bic_SR_register(SCG0); for (i=0; i<100; i++) { __delay_cycles(0xffff); } // check for oscillator fault while (SFRIFG1 & OFIFG) { UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT2OFFG); SFRIFG1 &= ~OFIFG; } SELECT_MCLK(SELM__DCOCLK); SELECT_ACLK(SELA__REFOCLK); SELECT_SMCLK(SELS__DCOCLK); UCSCTL7 = 0; // Errata UCS11 __bis_SR_register(srRegisterState); // Restore previous SCG0 }
void init_board(void) { PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on // default high-impedance mode // to activate previously // configured port settings //=== CPU speed // P4.1 and P4.2 drive the external crystal P4SEL0 |= 0x06; // switch on the crysyal oscillator do { CSCTL7 &= ~(XT1OFFG | DCOFFG); // Clear XT1 and DCO fault flag SFRIFG1&= ~OFIFG; } while (SFRIFG1 & OFIFG); // Test oscillator fault flag // slave the DCO to the crystal __bis_SR_register(SCG0); // disable FLL CSCTL3 |= SELREF__XT1CLK; // Set XT1CLK as FLL reference source CSCTL0 = 0; // clear DCO and MOD registers CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first CSCTL1 |= DCORSEL_3; // Set DCO = 8MHz CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz __delay_cycles(3); __bic_SR_register(SCG0); // enable FLL while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked // choose ACLK, MCLK and SMCLK speeds CSCTL4 = SELMS__DCOCLKDIV | SELA__XT1CLK; // Set ACLK = XT1CLK = 32768Hz // DCOCLK = MCLK and SMCLK source CSCTL5 |= DIVM_0 | DIVS_1; // MCLK = DCOCLK = 8MHZ, // SMCLK = MCLK/2 = 4MHz }
//***************************************************************************** // // 时钟初始化 // //***************************************************************************** void Osccon_Initial(void) { SetVCoreUp(PMMCOREV_3); // Set Vcore to accomodate for max. allowed system speed UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_7; // Select DCO range 24MHz operation UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz __bic_SR_register(SCG0); // Enable the FLL control loop P5SEL |= BIT2 + BIT3; // Port select XT2 UCSCTL6 &= ~XT2OFF; // Enable XT2 UCSCTL6 &= ~(XT1OFF); // XT1 On UCSCTL6 |= XCAP_3; // Internal load cap UCSCTL4 &= ~SELS_5; UCSCTL4 |= SELS_4; //SMCLKѡ��DCOCLKDIV (��Ƶ���Ƶ��) UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags delayms(800); UCSCTL6 &= ~XT2DRIVE0;// Decrease XT2 Drive according to expected frequency }
/**********************************************************************//** * @brief Set function for MCLK frequency. * * @param systemClockSpeed Intended frequency of operation - SYSCLK_xxMHZ. * * @return none *************************************************************************/ void halBoardSetSystemClock(unsigned char systemClockSpeed) { unsigned char setDcoRange, setVCore; unsigned int setMultiplier; halBoardGetSystemClockSettings( systemClockSpeed, &setDcoRange, \ &setVCore, &setMultiplier); halBoardSetVCore( setVCore ); __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x00; // Set lowest possible DCOx, MODx UCSCTL1 = setDcoRange; // Select suitable range UCSCTL2 = setMultiplier + FLLD_1; // Set DCO Multiplier UCSCTL4 = SELA__XT1CLK | SELS__DCOCLKDIV | SELM__DCOCLKDIV ; __bic_SR_register(SCG0); // Enable the FLL control loop // Loop until XT1,XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_FLL_reference. See UCS chapter in 5xx UG // for optimization. // 32 x 32 x / f_FLL_reference (32,768 Hz) = .03125 = t_DCO_settle // t_DCO_settle / (1 / 25 MHz) = 781250 = counts_DCO_settle __delay_cycles(781250); }
void config_clock(void) { /* SetVcoreUp (0x01); SetVcoreUp (0x02); SetVcoreUp (0x03); */ /* P2DIR |= BIT2; // SMCLK set out to pins P2SEL |= BIT2; */ UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO P5SEL |= BIT2 + BIT3; // Port select XT2 UCSCTL6 &= ~XT2OFF; // Enable XT2 __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // DCO=0, MOD=0 UCSCTL1 = DCORSEL_6; // Target DCO is 12Mhz = (2+1)*4MHz UCSCTL2 = FLLD_1 + 2; // DCO Mult N for 25MHz; Set FLLDiv D = fDCOCLK/1 UCSCTL3 = SELREF_5; // use XT2 reference __bic_SR_register(SCG0); // Enable the FLL control loop do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); SFRIFG1 &= ~OFIFG; } while (SFRIFG1 & OFIFG); UCSCTL6 &= ~XT2DRIVE0; } // enable_XT2()
void neopixel_draw() { int i, j; //uint8_t packet[3]; __bic_SR_register(GIE); for(i = 0; i < NUM_PIXELS; i++) { uint8_t packet[3] = {ledStrip[i].green,ledStrip[i].red, ledStrip[i].blue}; for(j = 0; j < 3; j++) { uint8_t mask = 0x80; while(mask != 0) { while(!(IFG2 & UCB0TXIFG)); if (packet[j] & mask) UCB0TXBUF = 0xF0; else UCB0TXBUF = 0xC0; mask >>= 1; } } } __delay_cycles(800); __bis_SR_register(GIE); }
void BCSplus_graceInit() { WDTCTL = WDTPW | WDTHOLD; SetVcoreUp (0x01); SetVcoreUp (0x02); SetVcoreUp (0x03); UCSCTL3 = SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_7; // Select DCO range 50MHz operation UCSCTL2 = FLLD_0 + 762; // Set DCO Multiplier for 25MHz __bic_SR_register(SCG0); // Enable the FLL control loop __delay_cycles(782000); // Loop until XT1,XT2 & DCO stabilizes - In this case only DCO has to stabilize do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag }
Void Boot_configureDCO(Void) { REG(UCSCTL3) |= SELREF_2; /* set FLL ref to REF0 */ REG(UCSCTL4) |= SELA_2; /* set ACLK to REF0 */ __bis_SR_register(SCG0); /* disable FLL */ REG(UCSCTL0) = 0x0000; /* set lowest DCOx and MODx bits */ REG(UCSCTL1) = DCORSEL_5; /* select 24 MHz range */ REG(UCSCTL2) = FLLD_1 + 249; /* * set multiplier for 8.192MHz: * (N + 1) * FLLRef = Fdco * (249 + 1) * 32768 = 8.192 MHz * FLL Div = fDCOCLK/2 */ __bic_SR_register(SCG0); /* enable FLL */ /* * worst-case settling time (MCLK cylces) * = N x 32 x 32 x f_MCLK / f_FLL_ref * * 250000 = 32 x 32 x 8 MHz / 32768 Hz */ __delay_cycles(250000); /* wait until XT1, XT2, and DCO fault flags are cleared... */ do { REG(UCSCTL7) &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); REG(SFRIFG1) &= ~OFIFG; } while (REG(SFRIFG1) &OFIFG); }
//***************************************************************************// // // // 初始化主时钟: MCLK = XT1×(FLL_FACTOR+1) 16Mhz // // // //***************************************************************************// void Init_CLK(void) { WDTCTL = WDTPW + WDTHOLD ; // 关看门狗 P7SEL |= 0x03 ; // 端口选择外部低频晶振XT1 UCSCTL6 &=~XT1OFF ; // 使能外部晶振 UCSCTL6 |= XCAP_3 ; // 设置内部负载电容 UCSCTL3 |= SELREF_0 ; // DCOref = REFO UCSCTL4 |= SELA_0 ; // ACLK = XT1 __bis_SR_register(SCG0) ; // 关闭FLL控制回路 UCSCTL0 = 0x0000 ; // 设置DCOx, MODx UCSCTL1 = DCORSEL_5 ; // 设置DCO振荡范围 UCSCTL2 = FLLD__1 + FLL_FACTOR_16M ; // Fdco = ( FLL_FACTOR + 1)×FLLRef = (649 + 1) * 32768 = 21.2992MHz __bic_SR_register(SCG0) ; // 打开FLL控制回路 __delay_cycles(1024000) ; do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // 清除 XT2,XT1,DCO 错误标志 SFRIFG1 &= ~OFIFG ; } while(SFRIFG1&OFIFG) ; // 检测振荡器错误标志 // ACK、MCK、SMCK输出至P11.0/1/2 /* //测试用 P11DS = TACK + TMCK + TSMCK ; P11SEL = TACK + TMCK + TSMCK ; P11DIR = TACK + TMCK + TSMCK ; while(1); */ }
static void board_set_clock_8_mhz(void) { P4SEL0 |= BIT1 | BIT2; // set XT1 pin as second function do { CSCTL7 &= ~(XT1OFFG | DCOFFG); // Clear XT1 and DCO fault flag SFRIFG1 &= ~OFIFG; }while (SFRIFG1 & OFIFG); // Test oscillator fault flag __bis_SR_register(SCG0); // disable FLLUNLOCK // CSCTL3 |= SELREF__REFOCLK; // No XTAL, so we set REFO (~32768kHz) // as FLL reference source CSCTL3 |= SELREF__REFOCLK; // 32786khz XTAL is present, so we use it // as FLL reference source CSCTL0 = 0; // clear DCO and MOD registers CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first CSCTL1 |= DCORSEL_3; // Set DCO = 8MHz CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz __delay_cycles(3); __bic_SR_register(SCG0); // enable FLL while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)) // Poll until FLL is locked ; CSCTL4 = SELMS__DCOCLKDIV | SELA__XT1CLK; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz // default DCODIV as MCLK and SMCLK source __delay_cycles(8000); }
void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop WDT // Setup UCS: ACLK = REFO; MCLK = SMCLK = 12MHz UCSCTL4 = SELA__REFOCLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV; UCSCTL3 |= SELREF__REFOCLK; // Set DCO FLL reference = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation UCSCTL2 = FLLD_1 + 374; // Set DCO Multiplier for 12MHz // (N + 1) * FLLRef = Fdco // (374 + 1) * 32768 = 12MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle __delay_cycles(375000); // Loop until XT1,XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag P2SEL |= BIT0; // Enable CB0 input // Setup ComparatorB CBCTL0 |= CBIPEN + CBIPSEL_0; // Enable V+, input channel CB0 CBCTL1 |= CBPWRMD_0; // CBMRVS=0 => select VREF1 as ref when CBOUT // is high and VREF0 when CBOUT is low // High-Speed Power mode CBCTL2 |= CBRSEL; // Ref is applied to -terminal CBCTL2 |= CBRS_1+CBREF13; // VREF1 is Vcc*1/4 CBCTL2 |= CBREF04+CBREF03; // VREF0 is Vcc*3/4 CBCTL3 |= BIT0; // Input Buffer Disable @P6.0/CB0 CBCTL1 |= CBON; // Turn On ComparatorB // Setup Timer_A0 and Timer_A1 // Internally CBOUT --> TA0CCTL1:CCIB (TA0.1) // +-> TA1CCTL1:CCIB (TA1.1) TA0CTL = TASSEL_2 + MC_1; // SMCLK, upmode TA1CTL = TASSEL_2 + MC_1; // SMCLK, upmode TA0CCR0 = 0xFFFF; TA1CCR0 = 0xFFFF; TA0CCTL1 = CM_2+SCS+CAP+CCIS_1; // Capture Falling Edge TA1CCTL1 = CM_1+SCS+CAP+CCIS_1+CCIE; // Capture Rising Edge, Enable Interrupt P1DIR |= BIT0; // Set P1.0/LED to output __bis_SR_register(LPM3_bits+GIE); // Enter LPM0 with global interrupts enabled __no_operation(); // For Debug }
void hal_cpu_disable_irqs(){ // LED off LED1_OUT &= ~LED1_PIN; // disable irq __bic_SR_register(GIE); }
void hal_cpu_disable_irqs(){ // LED off LED_PORT_OUT &= ~LED_1; // disable irq __bic_SR_register(GIE); }
void set_DCO_freq(unsigned char x){ UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL4 &= ~SELS_7; // Clear SMCLK default selection UCSCTL4 |= SELS__REFOCLK; // Set SMCLK = REFO __delay_cycles(250000); switch(x){ case 2: UCSCTL1 = DCORSEL_4; // Select DCO range 16MHz operation UCSCTL2 = FLLD_1 + 60; // Set DCO Multiplier for 8MHz break; // (N + 1) * FLLRef = Fdco // (244 + 1) * 32768 = 8MHz // Set FLL Div = fDCOCLK/2 break; case 4: UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation UCSCTL2 = FLLD_1 + 121; break; case 8: UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation UCSCTL2 = FLLD_1 + 243; break; case 12: UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation UCSCTL2 = FLLD_1 + 365; break; case 16: UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation UCSCTL2 = FLLD_1 + 487; break; default: break; } __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle __delay_cycles(250000); // Loop until XT1,XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag return; }
void Clock_Init(void) { // Setup Clock P5SEL |= BIT0 + BIT1; // Port select XT1 UCSCTL6 |= XCAP_3 + XT1OFF + XT2OFF; // Internal load cap // XT1 and XT2 off // Loop until XT1 & DCO stabilizes - In this case loop until XT1 and DCO settle do { UCSCTL7 &= ~(XT1LFOFFG + DCOFFG); // Clear XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag UCSCTL6 &= ~(XT1DRIVE_3); // Xtal is now stable, reduce drive // strength /* PMAPPWD = 0x02D52; // Get write-access to port mapping regs P2MAP0 = PM_ACLK; // Map ACLK output to P2.0 P2MAP2 = PM_MCLK; // Map MCLK output to P2.2 P2MAP4 = PM_SMCLK; // Map SMCLK output to P2.4 PMAPPWD = 0; // Lock port mapping registers */ P2DIR |= BIT0 + BIT2 + BIT4; // ACLK, MCLK, SMCLK set out to pins P2SEL |= BIT0 + BIT2 + BIT4; // P2.0,2,4 for debugging purposes. UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_7; // Select DCO range 20MHz operation UCSCTL2 = FLLD_1 + 614; // Set DCO Multiplier for 12MHz // (N + 1) * FLLRef = Fdco // (614 + 1) * 32768 = 20MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 20 MHz / 20,000 Hz = 625000 = MCLK cycles for DCO to settle __delay_cycles(625000); // Loop until XT1,XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag }
void msp430g2553_stopTimerA1(void) { __bic_SR_register(GIE); // Setting MCx = 00h when Timer_A is not in use conserves power. TBCTL &= (~(BIT4 | BIT5)); // Set MC_x to 0x0 TBCCR0 = 0x0; TBCCTL0 &= ~(CCIE | CCIFG); PLTFRM_timerSts &= ~PLTRM_TIMER_A1_ACTIVE_BIT; SYS_globalEvtMsk0 &= ~(SYS_GLOBAL_EVT_TIMER_A1_EXPIRY); __bis_SR_register(GIE); }
void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer PMAPPWD = 0x02D52; // Enable Write-access to modify port mapping registers P4MAP7 = PM_MCLK; PMAPPWD = 0; // Disable Write-Access to modify port mapping registers P1DIR |= BIT0; // ACLK set out to pins P1SEL |= BIT0; P4SEL |= BIT7; P4DIR |= BIT7; // MCLK set out to pins P5SEL |= BIT4+BIT5; // Port select XT1 UCSCTL6 &= ~(XT1OFF); // XT1 On UCSCTL6 |= XCAP_3; // Internal load cap // Loop until XT1 fault flag is cleared do { UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags }while (UCSCTL7&XT1LFOFFG); // Test XT1 fault flag // Initialize DCO to 2.45MHz __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_3; // Set RSELx for DCO = 4.9 MHz UCSCTL2 = FLLD_1 + 74; // Set DCO Multiplier for 2.45MHz // (N + 1) * FLLRef = Fdco // (74 + 1) * 32768 = 2.45MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 2.45 MHz / 32,768 Hz = 76563 = MCLK cycles for DCO to settle __delay_cycles(76563); // Loop until XT1,XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag while(1); // Loop in place }
void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer P1DIR |= BIT0; // P1.0 output P11DIR |= 0x07; // ACLK, MCLK, SMCLK set out to pins P11SEL |= 0x07; // P11.0,1,2 for debugging purposes. // Initialize LFXT1 P7SEL |= 0x03; // Select XT1 UCSCTL6 &= ~(XT1OFF); // XT1 On UCSCTL6 |= XCAP_3; // Internal load cap // Loop until XT1 fault flag is cleared do { UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags }while (UCSCTL7&XT1LFOFFG); // Test XT1 fault flag // Initialize DCO to 2.45MHz __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_3; // Set RSELx for DCO = 4.9 MHz UCSCTL2 = FLLD_1 + 74; // Set DCO Multiplier for 2.45MHz // (N + 1) * FLLRef = Fdco // (74 + 1) * 32768 = 2.45MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 2.45 MHz / 32,768 Hz = 76563 = MCLK cycles for DCO to settle __delay_cycles(76563); // Loop until XT1,XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag while(1) { P1OUT ^= BIT0; // Toggle P1.0 __delay_cycles(600000); // Delay } }
/// /// set dco features /// unsigned long int setDCO(unsigned long int mhz){ unsigned long int risultato; /// set almost high value in V_CORE /// set highest value of V_CORE if (mhz < 5000000) risultato = SetVCore(PMMCOREV_0); else if (mhz < 10000000) risultato = SetVCore(PMMCOREV_2); else risultato = SetVCore(PMMCOREV_3); risultato = mhz / 32768; UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx //UCSCTL1 = DCORSEL_2; // Select DCO range 0.3MHz - 7MHz operation /// set DCO range: 2.5 - 54 MHz UCSCTL1 = DCORSEL_5; //UCSCTL2 = FLLD_0 + 127; // Set DCO Multiplier for 4.1943MHz // (127 + 1) * FLLRef = Fdco // (127 + 1) * 32768 = 4.1943MHz // Set FLL Div = fDCOCLK/1 //UCSCTL2 = FLLD_0 + 511; // Set DCO Multiplier for 16.777216MHz // (511 + 1) * FLLRef = Fdco // (511 + 1) * 32768 = 16.777216MHz // Set FLL Div = fDCOCLK/1 UCSCTL2 = FLLD_0 + risultato - 1; // Set DCO Multiplier for 29.491200MHz // (899 + 1) * FLLRef = Fdco // (899 + 1) * 32768 = 29.491200MHz // Set FLL Div = fDCOCLK/1 __bic_SR_register(SCG0); // Enable the FLL control loop __delay_cycles(1375000); // Loop until XT1,XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); /// fine dell'impostazione del clock. return risultato; }
void main(void) { WDTCTL = WDTPW+WDTHOLD; // Stop WDT /* Initialize Ports */ P1DIR |= BIT0 + BIT6; // P1.0 output, P1.6 GND reference P1OUT = 0; PMAPPWD = 0x02D52; // Get write-access to port mapping regs P2MAP0 = PM_ACLK; // Map ACLK output to P2.0 P2MAP2 = PM_MCLK; // Map MCLK output to P2.2 P2MAP4 = PM_SMCLK; // Map SMCLK output to P2.4 PMAPPWD = 0; // Lock port mapping registers P2DIR |= BIT0 + BIT2 + BIT4; // ACLK, MCLK, SMCLK set out to pins P2SEL |= BIT0 + BIT2 + BIT4; // P2.0,2,4 for debugging purposes UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO UCSCTL4 |= SELA_2; // Set ACLK = REFO __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_5; // Select DCO range 16MHz operation UCSCTL2 = FLLD_1 + 249; // Set DCO Multiplier for 8MHz // (N + 1) * FLLRef = Fdco // (249 + 1) * 32768 = 8MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // Enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 8 MHz / 32,768 Hz = 250000 = MCLK cycles for DCO to settle __delay_cycles(250000); // Loop until XT1,XT2 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags }while (SFRIFG1&OFIFG); // Test oscillator fault flag while(1) { P1OUT ^= BIT0; // Toggle P1.0 __delay_cycles(600000); // Delay } }
void init_UCS(void) { //inicialització de les freqüències de rellotge del microcontrolador unsigned long DCORSEL = DCORSEL_7; //DCORSEL_7 selecciona rango de DCO de 8.5 a 19.6 MHz unsigned short FLLN = 487; //Parametro N __bis_SR_register(SCG0); // Desactiva el FLL control loop UCSCTL0 = 0x00; // Posa DCOx, MODx al mínim possible UCSCTL1 = DCORSEL; // Seleccionem el rang de DCO 16 MHz UCSCTL2 = FLLN + FLLD_1; //Selecciona el factor multiplicador del DCO UCSCTL3 = 0; //Referència FLL SELREF = XT1, divisor =1; /* Selecció de la font de rellotge: ACLK el Clock extern de 215, SMCLK i MCLK el DCO intern de 16MHz */ UCSCTL4 = SELA__XT1CLK | SELS__DCOCLKDIV | SELM__DCOCLKDIV; UCSCTL5 = DIVA__1 | DIVS__1; //Divisor per SMCLK: f(SMCLK)/1 i ACLK: f(ACLK)/1 __bic_SR_register(SCG0); // Enable the FLL control loop P11DIR = 0x07; //Configurem els pins 11.0, 11.1 y 11.2 com sortida P11SEL = 0x07; //ACLK, MCLK y SMCLK; activem els pins de test }