/**
\brief Test case: TC_CoreFunc_APSR
\details
- Check if __get_APSR intrinsic is available
- Check if __get_xPSR intrinsic is available
- Check negative, zero and overflow flags
*/
void TC_CoreFunc_APSR (void) {
uint32_t result;
//lint -esym(838, Rm) unused values
//lint -esym(438, Rm) unused values
// Check negative flag
int32_t Rm = 5;
int32_t Rn = 7;
SUBS(Rm, Rm, Rn);
result = __get_APSR();
ASSERT_TRUE((result & APSR_N_Msk) == APSR_N_Msk);
Rm = 5;
Rn = 7;
SUBS(Rm, Rm, Rn);
result = __get_xPSR();
ASSERT_TRUE((result & xPSR_N_Msk) == xPSR_N_Msk);
// Check zero and compare flag
Rm = 5;
SUBS(Rm, Rm, Rm);
result = __get_APSR();
ASSERT_TRUE((result & APSR_Z_Msk) == APSR_Z_Msk);
ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk);
Rm = 5;
SUBS(Rm, Rm, Rm);
result = __get_xPSR();
ASSERT_TRUE((result & xPSR_Z_Msk) == xPSR_Z_Msk);
ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk);
// Check overflow flag
Rm = 5;
Rn = INT32_MAX;
ADDS(Rm, Rm, Rn);
result = __get_APSR();
ASSERT_TRUE((result & APSR_V_Msk) == APSR_V_Msk);
Rm = 5;
Rn = INT32_MAX;
ADDS(Rm, Rm, Rn);
result = __get_xPSR();
ASSERT_TRUE((result & xPSR_V_Msk) == xPSR_V_Msk);
}
/**
\brief Test case: TC_CoreSimd_ParSel
\details
- Check Parallel selection:
__SEL
*/
void TC_CoreSimd_ParSel (void) {
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
volatile uint32_t res_u32;
volatile int32_t op1_s32, op2_s32;
volatile int32_t res_s32;
APSR_Type apsr;
xPSR_Type xpsr;
/* --- __SEL Test ---------------------------------------------- */
op1_s32 = 0x33221100;
op2_s32 = 0x77665544;
res_s32 = __SADD8(0x80808080, 0x00000000); /* __sadd8 sets APSR.GE = 0x00 */
res_u32 = __get_APSR();
apsr.w = __get_APSR();
ASSERT_TRUE( (res_u32 == apsr.w) );
xpsr.w = __get_xPSR();
ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) );
res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x00 */
ASSERT_TRUE( res_s32 == 0x77665544);
res_s32 = __SADD8(0x80808000, 0x00000000); /* __sadd8 sets APSR.GE = 0x01 */
res_u32 = __get_APSR();
apsr.w = __get_APSR();
ASSERT_TRUE( (res_u32 == apsr.w) );
xpsr.w = __get_xPSR();
ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) );
res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x01 */
ASSERT_TRUE(res_s32 == 0x77665500);
res_s32 = __SADD8(0x80800080, 0x00000000); /* __sadd8 sets APSR.GE = 0x02 */
res_u32 = __get_APSR();
apsr.w = __get_APSR();
ASSERT_TRUE( (res_u32 == apsr.w) );
xpsr.w = __get_xPSR();
ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) );
res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x02 */
ASSERT_TRUE(res_s32 == 0x77661144);
#endif
}
/*!
* \brief An MQX-provided default ISR for unhandled interrupts. The function
* depends on the PSP.
*
* The function changes the state of the active task to UNHANDLED_INT_BLOCKED and
* blocks the task.
* \n The function uses the default I/O channel to display at least:
* \li Vector number that caused the unhandled exception.
* \li Task ID and task descriptor of the active task.
*
* \n Depending on the PSP, more information might be displayed.
*
* \param[in] parameter Parameter passed to the default ISR.
*
* \note
* Since the ISR uses printf() to display information to the default I/O channel,
* default I/O must not be on a channel that uses interrupt-driven I/O or the
* debugger.
*
* \warning Blocks the active task.
*
* \see _int_install_unexpected_isr
*/
void _int_unexpected_isr
(
void *parameter
)
{ /* Body */
KERNEL_DATA_STRUCT_PTR kernel_data;
TD_STRUCT_PTR td_ptr;
_GET_KERNEL_DATA(kernel_data);
td_ptr = kernel_data->ACTIVE_PTR;
#if MQXCFG_PRINT_MEM_DUMP
#error "MQXCFG_PRINT_MEM_DUMP functionality is currently not supported. This feature will be supported again in future release.\
Please set MQXCFG_PRINT_MEM_DUMP to zero."
#endif
#if MQXCFG_PRINT_MEM_DUMP
{
unsigned int psp, msp, i;
printf("\n\r*** UNHANDLED INTERRUPT ***\n\r");
printf("Vector #: 0x%02x Task Id: 0x%0x Td_ptr 0x%x\n\r",
(unsigned int)parameter, (unsigned int)td_ptr->TASK_ID, (unsigned int)td_ptr);
psp = __get_PSP();
msp = __get_MSP();
printf("PSP: 0x%08x MSP: 0x%08x PSR: 0x%08x\n\r", psp, msp, (unsigned int)__get_xPSR());
printf("\n\r\n\rMemory dump:\n\r");
for (i = 0; i < 32; i += 4) {
printf("0x%08x : 0x%08x 0x%08x 0x%08x 0x%08x\n\r", psp + i * 4, ((unsigned int*)psp)[i], ((unsigned int*)psp)[i + 1], ((unsigned int*)psp)[i + 2], ((unsigned int*)psp)[i + 3]);
}
printf("\n\r\n\rMemory dump:\n\r");
for (i = 0; i < 32; i += 4) {
printf("0x%08x : 0x%08x 0x%08x 0x%08x 0x%08x\n\r", msp + i * 4, ((unsigned int*)msp)[i], ((unsigned int*)msp)[i + 1], ((unsigned int*)msp)[i + 2], ((unsigned int*)msp)[i + 3]);
}
}
#endif /* MQXCFG_PRINT_MEM_DUMP */
_INT_DISABLE();
if (td_ptr->STATE != UNHANDLED_INT_BLOCKED) {
td_ptr->STATE = UNHANDLED_INT_BLOCKED;
td_ptr->INFO = (_mqx_uint)parameter;
_QUEUE_UNLINK(td_ptr);
} /* Endif */
_INT_ENABLE();
} /* Endbody */
/**
\brief Test case: TC_CoreFunc_IPSR
\details
- Check if __get_IPSR intrinsic is available
- Check if __get_xPSR intrinsic is available
- Result differentiates between thread and exception modes
*/
void TC_CoreFunc_IPSR (void) {
uint32_t result = __get_IPSR();
ASSERT_TRUE(result == 0U); // Thread Mode
result = __get_xPSR();
ASSERT_TRUE((result & xPSR_ISR_Msk) == 0U); // Thread Mode
TST_IRQHandler = TC_CoreFunc_IPSR_IRQHandler;
irqIPSR = 0U;
irqXPSR = 0U;
NVIC_ClearPendingIRQ(WDT_IRQn);
NVIC_EnableIRQ(WDT_IRQn);
__enable_irq();
NVIC_SetPendingIRQ(WDT_IRQn);
for(uint32_t i = 10U; i > 0U; --i) {}
__disable_irq();
NVIC_DisableIRQ(WDT_IRQn);
ASSERT_TRUE(irqIPSR != 0U); // Exception Mode
ASSERT_TRUE((irqXPSR & xPSR_ISR_Msk) != 0U); // Exception Mode
}
static void TC_CoreFunc_IPSR_IRQHandler(void) {
irqIPSR = __get_IPSR();
irqXPSR = __get_xPSR();
}
