static void __init gic_clocksource_of_init(struct device_node *node) { struct clk *clk; if (WARN_ON(!gic_present || !node->parent || !of_device_is_compatible(node->parent, "mti,gic"))) return; clk = of_clk_get(node, 0); if (!IS_ERR(clk)) { gic_frequency = clk_get_rate(clk); clk_put(clk); } else if (of_property_read_u32(node, "clock-frequency", &gic_frequency)) { pr_err("GIC frequency not specified.\n"); return; } gic_timer_irq = irq_of_parse_and_map(node, 0); if (!gic_timer_irq) { pr_err("GIC timer IRQ not specified.\n"); return; } __gic_clocksource_init(); }
void __init gic_clocksource_init(unsigned int frequency) { gic_frequency = frequency; gic_timer_irq = MIPS_GIC_IRQ_BASE + GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE); __gic_clocksource_init(); }
void __init gic_clocksource_init(unsigned int frequency) { gic_frequency = frequency; gic_timer_irq = MIPS_GIC_IRQ_BASE + GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE); __gic_clocksource_init(); gic_clockevent_init(); /* And finally start the counter */ gic_start_count(); }
static int __init gic_clocksource_of_init(struct device_node *node) { struct clk *clk; int ret; if (!mips_gic_present() || !node->parent || !of_device_is_compatible(node->parent, "mti,gic")) { pr_warn("No DT definition\n"); return -ENXIO; } clk = of_clk_get(node, 0); if (!IS_ERR(clk)) { ret = clk_prepare_enable(clk); if (ret < 0) { pr_err("Failed to enable clock\n"); clk_put(clk); return ret; } gic_frequency = clk_get_rate(clk); } else if (of_property_read_u32(node, "clock-frequency", &gic_frequency)) { pr_err("Frequency not specified\n"); return -EINVAL; } gic_timer_irq = irq_of_parse_and_map(node, 0); if (!gic_timer_irq) { pr_err("IRQ not specified\n"); return -EINVAL; } ret = __gic_clocksource_init(); if (ret) return ret; ret = gic_clockevent_init(); if (!ret && !IS_ERR(clk)) { if (clk_notifier_register(clk, &gic_clk_nb) < 0) pr_warn("Unable to register clock notifier\n"); } /* And finally start the counter */ clear_gic_config(GIC_CONFIG_COUNTSTOP); return 0; }