static int omap2_iommu_enable(struct omap_iommu *obj) { u32 l, pa; /* * HACK: without this, we blow imprecise external abort on uEVM * followed by L3 bus exception spew */ if (cpu_is_omap54xx()) { pr_info("omap2_iommu_enable: doing Benelli reset HACK\n"); __raw_writel(3, OMAP2_L4_IO_ADDRESS(0x4AE06910)); /* We need some ugly wait here as reread or mb() are not * sufficient... */ mdelay(500); } if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) return -EINVAL; pa = virt_to_phys(obj->iopgd); if (!IS_ALIGNED(pa, SZ_16K)) return -EINVAL; l = iommu_read_reg(obj, MMU_REVISION); dev_info(obj->dev, "%s: version %d.%d\n", obj->name, (l >> 4) & 0xf, l & 0xf); iommu_write_reg(obj, pa, MMU_TTB); __iommu_set_twl(obj, true); return 0; }
static int omap2_iommu_enable(struct omap_iommu *obj) { u32 l, pa; struct iommu_platform_data *pdata = obj->dev->platform_data; if (!obj->secure_mode) { if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) return -EINVAL; pa = virt_to_phys(obj->iopgd); if (!IS_ALIGNED(pa, SZ_16K)) return -EINVAL; } else { pa = (u32)obj->secure_ttb; if (!pa || !IS_ALIGNED(pa, SZ_16K)) return -EINVAL; } l = iommu_read_reg(obj, MMU_REVISION); dev_info(obj->dev, "%s: version %d.%d\n", obj->name, (l >> 4) & 0xf, l & 0xf); iommu_write_reg(obj, pa, MMU_TTB); __iommu_set_twl(obj, true); if (pdata->has_bus_err_back) iommu_write_reg(obj, MMU_BUS_ERR_BACK_EN, MMU_GP_REG); return 0; }
static int omap2_iommu_enable(struct omap_iommu *obj) { u32 l, pa; if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) return -EINVAL; pa = virt_to_phys(obj->iopgd); if (!IS_ALIGNED(pa, SZ_16K)) return -EINVAL; l = iommu_read_reg(obj, MMU_REVISION); dev_info(obj->dev, "%s: version %d.%d\n", obj->name, (l >> 4) & 0xf, l & 0xf); iommu_write_reg(obj, pa, MMU_TTB); dra7_cfg_dspsys_mmu(obj, true); if (obj->has_bus_err_back) iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG); __iommu_set_twl(obj, true); return 0; }
static int omap2_iommu_enable(struct iommu *obj) { u32 l, pa; unsigned long timeout; if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) return -EINVAL; pa = virt_to_phys(obj->iopgd); if (!IS_ALIGNED(pa, SZ_16K)) return -EINVAL; iommu_write_reg(obj, MMU_SYS_SOFTRESET, MMU_SYSCONFIG); timeout = jiffies + msecs_to_jiffies(20); do { l = iommu_read_reg(obj, MMU_SYSSTATUS); if (l & MMU_SYS_RESETDONE) break; } while (!time_after(jiffies, timeout)); if (!(l & MMU_SYS_RESETDONE)) { dev_err(obj->dev, "can't take mmu out of reset\n"); return -ENODEV; } l = iommu_read_reg(obj, MMU_REVISION); dev_info(obj->dev, "%s: version %d.%d\n", obj->name, (l >> 4) & 0xf, l & 0xf); l = iommu_read_reg(obj, MMU_SYSCONFIG); l &= ~MMU_SYS_IDLE_MASK; l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE); iommu_write_reg(obj, l, MMU_SYSCONFIG); iommu_write_reg(obj, pa, MMU_TTB); __iommu_set_twl(obj, true); return 0; }
static int omap2_iommu_enable(struct omap_iommu *obj) { u32 l, pa; if (!obj->iopgd || !IS_ALIGNED((u32)obj->iopgd, SZ_16K)) return -EINVAL; pa = virt_to_phys(obj->iopgd); if (!IS_ALIGNED(pa, SZ_16K)) return -EINVAL; l = iommu_read_reg(obj, MMU_REVISION); dev_info(obj->dev, "%s: version %d.%d\n", obj->name, (l >> 4) & 0xf, l & 0xf); iommu_write_reg(obj, pa, MMU_TTB); __iommu_set_twl(obj, true); return 0; }
static void omap2_iommu_set_twl(struct iommu *obj, bool on) { __iommu_set_twl(obj, false); }