void iwl_clear_bit(struct iwl_bus *bus, u32 reg, u32 mask) { unsigned long flags; spin_lock_irqsave(&bus->reg_lock, flags); __iwl_clear_bit(bus, reg, mask); spin_unlock_irqrestore(&bus->reg_lock, flags); }
void iwl_release_nic_access(struct iwl_trans *trans) { lockdep_assert_held(&trans->reg_lock); __iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); /* * Above we read the CSR_GP_CNTRL register, which will flush * any previous writes, but we need the write that clears the * MAC_ACCESS_REQ bit to be performed before any other writes * scheduled on different CPUs (after we drop reg_lock). */ mmiowb(); }
void iwl_release_nic_access(struct iwl_bus *bus) { lockdep_assert_held(&bus->reg_lock); __iwl_clear_bit(bus, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); }