void vm_rewind_rip(offset_t offset)
{
if(__lmode64())
__rip.raw -= (uint64_t)offset;
else if(__pmode32())
__rip.low -= (uint32_t)offset;
else
__rip.wlow -= (uint16_t)offset;
__post_access(__rip);
}
static void gdb_cmd_rd_gpr()
{
size_t flen, vlen, ngpr, i;
if(__lmode64())
{
ngpr = 16;
vlen = sizeof(uint64_t)*2;
}
else
{
/* XXX: gdb seems to wait for 32 bits regs at least */
ngpr = 8;
vlen = sizeof(uint32_t)*2;
}
flen = sizeof(uint32_t)*2;
/* [r/e]ax - [r/e]di */
for(i=GPR64_RAX ; i >= ((GPR64_RAX+1)-ngpr) ; i--)
gdb_add_number(info->vm.cpu.gpr->raw[i].raw, vlen, 1);
/* [r/e]ip */
gdb_add_number(__rip.raw, vlen, 1);
/* fixed length eflags, cs, ss, ds, es, fs, gs */
gdb_add_number(__rflags.raw, flen, 1);
gdb_add_number(__cs.selector.raw, flen, 1);
__pre_access(__ss.selector); gdb_add_number(__ss.selector.raw, flen, 1);
__pre_access(__ds.selector); gdb_add_number(__ds.selector.raw, flen, 1);
__pre_access(__es.selector); gdb_add_number(__es.selector.raw, flen, 1);
__pre_access(__fs.selector); gdb_add_number(__fs.selector.raw, flen, 1);
__pre_access(__gs.selector); gdb_add_number(__gs.selector.raw, flen, 1);
gdb_send_packet();
}
/*
** Take care of lmode/compatmode/legacymode differences
** cf. table-2.6 (page 39) of amd manual
** cf. table 14-4 (page 358) of amd manual
**
** notice that instruction prefix can change these defaults
** addr/operand sizes
*/
static void __vm_resolve_seg_offset(offset_t *vaddr, offset_t base, offset_t offset,
offset_t addend, int *mode)
{
if(__lmode64())
{
*mode = 64;
*vaddr = offset + addend;
}
else
{
*vaddr = (base & 0xffffffff);
if(__pmode32())
{
*mode = 32;
*vaddr += (offset & 0xffffffff) + (addend & 0xffffffff);
}
else
{
*mode = 16;
*vaddr += (offset & 0xffff) + (addend & 0xffff);
}
}
}
