void __attribute__ ((optimize("Os"))) __cpu_init() { unsigned int tmp; /* turn on BTB */ tmp = 0x0; __nds32__mtsr(tmp, NDS32_SR_MISC_CTL); #if defined(NDS32_BASELINE_V3M) && defined(USE_C_EXT) /* set IVIC, vector size: 16 bytes, base: 0x0 * If we use v3m toolchain and want to use * C extension please use USE_C_EXT in CFLAGS */ __nds32__mtsr(0x4001, NDS32_SR_IVB); #else /* set IVIC, vector size: 4 bytes, base: 0x0 * If we use v3m toolchain and want to use * assembly version please don't use USE_C_EXT * in CFLAGS */ __nds32__mtsr(0x0, NDS32_SR_IVB); #endif /* Set PSW INTL to 0 */ tmp = __nds32__mfsr(NDS32_SR_PSW); tmp = tmp & 0xfffffff9; #if (defined(NDS32_BASELINE_V3M) || defined(NDS32_BASELINE_V3)) /* Set PSW CPL to 7 to allow any priority */ tmp = tmp | 0x70008; #endif __nds32__mtsr(tmp, NDS32_SR_PSW); __nds32__dsb(); #if (defined(NDS32_BASELINE_V3M) || defined(NDS32_BASELINE_V3)) /* Set PPL2FIX_EN to 0 to enable Programmable * Priority Level */ __nds32__mtsr(0x0, NDS32_SR_INT_CTRL); /* set priority HW0: 0, HW1: 1, HW2: 2, HW3: 3 * HW4-: 0 */ __nds32__mtsr(0xe4, NDS32_SR_INT_PRI); #endif /* enable FPU if the CPU support FPU */ #if defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP) tmp = __nds32__mfsr(NDS32_SR_FUCOP_EXIST); if ((tmp & 0x80000001) == 0x80000001) { tmp = __nds32__mfsr(NDS32_SR_FUCOP_CTL); __nds32__mtsr((tmp | 0x1), NDS32_SR_FUCOP_CTL); } #endif return; }
static void nds32_suspend2ram(void) { pgd_t *pgdv; pud_t *pudv; pmd_t *pmdv; pte_t *ptev; pgdv = (pgd_t *)__va((__nds32__mfsr(NDS32_SR_L1_PPTB) & L1_PPTB_mskBASE)) + pgd_index((unsigned int)cpu_resume); pudv = pud_offset(pgdv, (unsigned int)cpu_resume); pmdv = pmd_offset(pudv, (unsigned int)cpu_resume); ptev = pte_offset_map(pmdv, (unsigned int)cpu_resume); resume_addr = ((*ptev) & TLB_DATA_mskPPN) | ((unsigned int)cpu_resume & 0x00000fff); suspend2ram(); }
/* * mask/unmask priority >= _irqs_ interrupts * used in ISR & gie diable */ uint32_t hal_intc_irq_mask(int _irqs_) { uint32_t prv_msk = __nds32__mfsr(NDS32_SR_INT_MASK2); if (_irqs_ == -1 ) { __nds32__mtsr(0, NDS32_SR_INT_MASK2); } else if (_irqs_ < 32 ) { SR_CLRB32(NDS32_SR_INT_MASK2,_irqs_); } else { DEBUG(1,1,"_irqs_:%d, is invalid!\r\n",_irqs_); return -1; } return prv_msk; }
/* * All AE210P hardware initialization */ void hardware_init(void) { mmu_init(); /* mmu/cache */ plf_init(); /* Perform any platform specific initializations */ #if (defined(CONFIG_CPU_ICACHE_ENABLE) || defined(CONFIG_CPU_DCACHE_ENABLE)) unsigned int reg; /* Invalid ICache */ nds32_icache_flush(); /* Invalid DCache */ nds32_dcache_invalidate(); /* Enable I/Dcache */ reg = (__nds32__mfsr(NDS32_SR_CACHE_CTL) & ~CACHE_CTL_MSK) | CACHE_CTL_CACHE_ON; __nds32__mtsr(reg, NDS32_SR_CACHE_CTL); #endif }
static void nds32_suspend_cpu(void) { while (!(__nds32__mfsr(NDS32_SR_INT_PEND) & wake_mask)) __asm__ volatile ("standby no_wake_grant\n\t"); }
uint32_t hal_intc_get_all_pend() { return __nds32__mfsr(NDS32_SR_INT_PEND2); }