static int xicor_read(uint8_t addr) { while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD)); __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA)); __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, SMB_CSR(R_SMB_START)); while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, SMB_CSR(R_SMB_START)); while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff); }
static int m41t81_write(uint8_t addr, int b) { while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD)); __raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA)); __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_WR2BYTE, SMB_CSR(R_SMB_START)); while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } /* read the same byte again to make sure it is written */ __raw_writeq(V_SMB_ADDR(M41T81_CCR_ADDRESS) | V_SMB_TT_RD1BYTE, SMB_CSR(R_SMB_START)); while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; return 0; }
static void dw8250_serial_outq(struct uart_port *p, int offset, int value) { struct dw8250_data *d = p->private_data; if (offset == UART_MCR) d->last_mcr = value; value &= 0xff; __raw_writeq(value, p->membase + (offset << p->regshift)); /* Read back to ensure register write ordering. */ __raw_readq(p->membase + (UART_LCR << p->regshift)); /* Make sure LCR write wasn't ignored */ if (offset == UART_LCR) { int tries = 1000; while (tries--) { unsigned int lcr = p->serial_in(p, UART_LCR); if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) return; dw8250_force_idle(p); __raw_writeq(value & 0xff, p->membase + (UART_LCR << p->regshift)); } /* * FIXME: this deadlocks if port->lock is already held * dev_err(p->dev, "Couldn't set LCR to %d\n", value); */ } }
/* * Bring up the timer at 100 Hz. */ void __init swarm_time_init(void) { unsigned int flags; int status; /* Set up the scd general purpose timer 0 to cpu 0 */ sb1250_time_init(); /* Establish communication with the Xicor 1241 RTC */ /* XXXKW how do I share the SMBus with the I2C subsystem? */ __raw_writeq(K_SMB_FREQ_400KHZ, SMB_CSR(R_SMB_FREQ)); __raw_writeq(0, SMB_CSR(R_SMB_CONTROL)); if ((status = xicor_read(X1241REG_SR_RTCF)) < 0) { printk("x1241: couldn't detect on SWARM SMBus 1\n"); } else { if (status & X1241REG_SR_RTCF) printk("x1241: battery failed -- time is probably wrong\n"); write_seqlock_irqsave(&xtime_lock, flags); xtime.tv_sec = get_swarm_time(); xtime.tv_nsec = 0; write_sequnlock_irqrestore(&xtime_lock, flags); } }
/* * The general purpose timer ticks at 1MHz independent if * the rest of the system */ static void sibyte_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { unsigned int cpu = smp_processor_id(); void __iomem *cfg, *init; cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); switch (mode) { case CLOCK_EVT_MODE_PERIODIC: __raw_writeq(0, cfg); __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); break; case CLOCK_EVT_MODE_ONESHOT: /* Stop the timer until we actually program a shot */ case CLOCK_EVT_MODE_SHUTDOWN: __raw_writeq(0, cfg); break; case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */ case CLOCK_EVT_MODE_RESUME: ; } }
static void disable_hub_irq(struct irq_data *d) { struct hub_irq_data *hd = irq_data_get_irq_chip_data(d); unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu); clear_bit(hd->bit, mask); __raw_writeq(mask[0], hd->irq_mask[0]); __raw_writeq(mask[1], hd->irq_mask[1]); }
static int sibyte_set_periodic(struct clock_event_device *evt) { unsigned int cpu = smp_processor_id(); void __iomem *cfg, *init; cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); __raw_writeq(0, cfg); __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); return 0; }
/** * mc_write_command - writes a command to a Management Complex (MC) portal * * @portal: pointer to an MC portal * @cmd: pointer to a filled command */ static inline void mc_write_command(struct mc_command __iomem *portal, struct mc_command *cmd) { int i; /* copy command parameters into the portal */ for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++) __raw_writeq(cmd->params[i], &portal->params[i]); __iowmb(); /* submit the command by writing the header */ __raw_writeq(cmd->header, &portal->header); }
static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd) { unsigned int cpu = smp_processor_id(); void __iomem *cfg, *init; cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); __raw_writeq(0, cfg); __raw_writeq(delta - 1, init); __raw_writeq(M_SCD_TIMER_ENABLE, cfg); return 0; }
void sb1_dma_init(void) { int i; for (i = 0; i < DM_NUM_CHANNELS; i++) { const u64 base_val = CPHYSADDR((unsigned long)&page_descr[i]) | V_DM_DSCR_BASE_RINGSZ(1); void *base_reg = IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE)); __raw_writeq(base_val, base_reg); __raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg); __raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, base_reg); } }
static void c2_tx_clean(struct c2_port *c2_port) { struct c2_ring *tx_ring = &c2_port->tx_ring; struct c2_element *elem; struct c2_txp_desc txp_htxd; int retry; unsigned long flags; spin_lock_irqsave(&c2_port->tx_lock, flags); elem = tx_ring->start; do { retry = 0; do { txp_htxd.flags = readw(elem->hw_desc + C2_TXP_FLAGS); if (txp_htxd.flags == TXP_HTXD_READY) { retry = 1; __raw_writew(0, elem->hw_desc + C2_TXP_LEN); __raw_writeq(0, elem->hw_desc + C2_TXP_ADDR); __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_DONE), elem->hw_desc + C2_TXP_FLAGS); c2_port->netdev->stats.tx_dropped++; break; } else { __raw_writew(0, elem->hw_desc + C2_TXP_LEN); __raw_writeq((__force u64) cpu_to_be64(0x1122334455667788ULL), elem->hw_desc + C2_TXP_ADDR); __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_UNINIT), elem->hw_desc + C2_TXP_FLAGS); } c2_tx_free(c2_port->c2dev, elem); } while ((elem = elem->next) != tx_ring->start); } while (retry); c2_port->tx_avail = c2_port->tx_ring.count - 1; c2_port->c2dev->cur_tx = tx_ring->to_use - tx_ring->start; if (c2_port->tx_avail > MAX_SKB_FRAGS + 1) netif_wake_queue(c2_port->netdev); spin_unlock_irqrestore(&c2_port->tx_lock, flags); }
static void ack_bcm1480_irq(unsigned int irq) { u64 pending; unsigned int irq_dirty; int k; /* * If the interrupt was an HT interrupt, now is the time to * clear it. NOTE: we assume the HT bridge was set up to * deliver the interrupts to all CPUs (which makes affinity * changing easier for us) */ irq_dirty = irq; if ((irq_dirty >= BCM1480_NR_IRQS_HALF) && (irq_dirty <= BCM1480_NR_IRQS)) { irq_dirty -= BCM1480_NR_IRQS_HALF; } for (k=0; k<2; k++) { /* Loop through high and low LDT interrupts */ pending = __raw_readq(IOADDR(A_BCM1480_IMR_REGISTER(bcm1480_irq_owner[irq], R_BCM1480_IMR_LDT_INTERRUPT_H + (k*BCM1480_IMR_HL_SPACING)))); pending &= ((u64)1 << (irq_dirty)); if (pending) { #ifdef CONFIG_SMP int i; for (i=0; i<NR_CPUS; i++) { /* * Clear for all CPUs so an affinity switch * doesn't find an old status */ __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(cpu_logical_map(i), R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); } #else __raw_writeq(pending, IOADDR(A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_LDT_INTERRUPT_CLR_H + (k*BCM1480_IMR_HL_SPACING)))); #endif /* * Generate EOI. For Pass 1 parts, EOI is a nop. For * Pass 2, the LDT world may be edge-triggered, but * this EOI shouldn't hurt. If they are * level-sensitive, the EOI is required. */ #ifdef CONFIG_PCI if (ht_eoi_space) *(uint32_t *)(ht_eoi_space+(irq<<16)+(7<<2)) = 0; #endif } } bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); }
void sb1250_time_init(void) { int cpu = smp_processor_id(); int irq = K_INT_TIMER_0+cpu; /* Only have 4 general purpose timers */ if (cpu > 3) { BUG(); } if (!cpu) { /* Use our own gettimeoffset() routine */ do_gettimeoffset = sb1250_gettimeoffset; } sb1250_mask_irq(cpu, irq); /* Map the timer interrupt to ip[4] of this cpu */ __raw_writeq(IMR_IP4_VAL, IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + (irq << 3))); /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */ /* Disable the timer and set up the count */ __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); #ifdef CONFIG_SIMULATION __raw_writeq(50000 / HZ, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #else __raw_writeq(1000000 / HZ, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #endif /* Set the timer running */ __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); sb1250_unmask_irq(cpu, irq); sb1250_steal_irq(irq); /* * This interrupt is "special" in that it doesn't use the request_irq * way to hook the irq line. The timer interrupt is initialized early * enough to make this a major pain, and it's also firing enough to * warrant a bit of special case code. sb1250_timer_interrupt is * called directly from irq_handler.S when IP[4] is set during an * interrupt */ }
void copy_page(void *to, void *from) { u64 from_phys = CPHYSADDR((unsigned long)from); u64 to_phys = CPHYSADDR((unsigned long)to); unsigned int cpu = smp_processor_id(); /* if any page is not in KSEG0, use old way */ if ((long)KSEGX((unsigned long)to) != (long)CKSEG0 || (long)KSEGX((unsigned long)from) != (long)CKSEG0) return copy_page_cpu(to, from); page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT; page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE); __raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT))); /* * Don't really want to do it this way, but there's no * reliable way to delay completion detection. */ while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG))) & M_DM_DSCR_BASE_INTERRUPT)) ; __raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE))); }
/** * octeon_i2c_write_int - write the TWSI_INT register * @i2c: The struct octeon_i2c. * @data: Value to be written. */ static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) { u64 tmp; __raw_writeq(data, i2c->twsi_base + TWSI_INT); tmp = __raw_readq(i2c->twsi_base + TWSI_INT); }
static void c2_rx_clean(struct c2_port *c2_port) { struct c2_dev *c2dev = c2_port->c2dev; struct c2_ring *rx_ring = &c2_port->rx_ring; struct c2_element *elem; struct c2_rx_desc *rx_desc; elem = rx_ring->start; do { rx_desc = elem->ht_desc; rx_desc->len = 0; __raw_writew(0, elem->hw_desc + C2_RXP_STATUS); __raw_writew(0, elem->hw_desc + C2_RXP_COUNT); __raw_writew(0, elem->hw_desc + C2_RXP_LEN); __raw_writeq((__force u64) cpu_to_be64(0x99aabbccddeeffULL), elem->hw_desc + C2_RXP_ADDR); __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_UNINIT), elem->hw_desc + C2_RXP_FLAGS); if (elem->skb) { pci_unmap_single(c2dev->pcidev, elem->mapaddr, elem->maplen, PCI_DMA_FROMDEVICE); dev_kfree_skb(elem->skb); elem->skb = NULL; } } while ((elem = elem->next) != rx_ring->start); }
static void dw8250_check_lcr(struct uart_port *p, int value) { void __iomem *offset = p->membase + (UART_LCR << p->regshift); int tries = 1000; /* Make sure LCR write wasn't ignored */ while (tries--) { unsigned int lcr = p->serial_in(p, UART_LCR); if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) return; dw8250_force_idle(p); #ifdef CONFIG_64BIT if (p->type == PORT_OCTEON) __raw_writeq(value & 0xff, offset); else #endif if (p->iotype == UPIO_MEM32) writel(value, offset); else if (p->iotype == UPIO_MEM32BE) iowrite32be(value, offset); else writeb(value, offset); } /* * FIXME: this deadlocks if port->lock is already held * dev_err(p->dev, "Couldn't set LCR to %d\n", value); */ }
void __init sb1250_clocksource_init(void) { struct clocksource *cs = &bcm1250_clocksource; /* Setup hpt using timer #3 but do not enable irq for it */ __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); __raw_writeq(SB1250_HPT_VALUE, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT))); __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); <<<<<<< HEAD
/* * set the initial count value of a timer * * wdog is the iomem address of the cfg register */ void sbwdog_set(char __iomem *wdog, unsigned long t) { spin_lock(&sbwd_lock); __raw_writeb(0, wdog); __raw_writeq(t & 0x7fffffUL, wdog - 0x10); spin_unlock(&sbwd_lock); }
void __init sb1250_clocksource_init(void) { struct clocksource *cs = &bcm1250_clocksource; __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); __raw_writeq(SB1250_HPT_VALUE, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT))); __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); clocksource_register_hz(cs, V_SCD_TIMER_FREQ); }
/** * octeon_i2c_reg_write - write an I2C core register * @i2c: The struct octeon_i2c * @eop_reg: Register selector * @data: Value to be written * * The I2C core registers are accessed indirectly via the SW_TWSI CSR. */ static void octeon_i2c_reg_write(struct octeon_i2c *i2c, u64 eop_reg, u8 data) { u64 tmp; __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI); do { tmp = __raw_readq(i2c->twsi_base + SW_TWSI); } while ((tmp & SW_TWSI_V) != 0); }
void __init arch_init_irq(void) { unsigned int i; u64 tmp; unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 | STATUSF_IP1 | STATUSF_IP0; /* Default everything to IP2 */ for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */ __raw_writeq(IMR_IP2_VAL, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + (i << 3))); __raw_writeq(IMR_IP2_VAL, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + (i << 3))); } init_sb1250_irqs(); /* * Map the high 16 bits of the mailbox registers to IP[3], for * inter-cpu messages */ /* Was I1 */ __raw_writeq(IMR_IP3_VAL, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) + (K_INT_MBOX_0 << 3))); __raw_writeq(IMR_IP3_VAL, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) + (K_INT_MBOX_0 << 3))); /* Clear the mailboxes. The firmware may leave them dirty */ __raw_writeq(0xffffffffffffffffULL, IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU))); __raw_writeq(0xffffffffffffffffULL, IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU))); /* Mask everything except the mailbox registers for both cpus */ tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0); __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK))); __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK))); /* * Note that the timer interrupts are also mapped, but this is * done in sb1250_time_init(). Also, the profiling driver * does its own management of IP7. */ /* Enable necessary IPs, disable the rest */ change_c0_status(ST0_IM, imask); }
/* * "memset" on IO memory space. */ void _memset_c_io(volatile void __iomem *to, unsigned long c, long count) { /* Handle any initial odd byte */ if (count > 0 && ((u64)to & 1)) { __raw_writeb(c, to); to++; count--; } /* Handle any initial odd halfword */ if (count >= 2 && ((u64)to & 2)) { __raw_writew(c, to); to += 2; count -= 2; } /* Handle any initial odd word */ if (count >= 4 && ((u64)to & 4)) { __raw_writel(c, to); to += 4; count -= 4; } /* Handle all full-sized quadwords: we're aligned (or have a small count) */ count -= 8; if (count >= 0) { do { __raw_writeq(c, to); to += 8; count -= 8; } while (count >= 0); } count += 8; /* The tail is word-aligned if we still have count >= 4 */ if (count >= 4) { __raw_writel(c, to); to += 4; count -= 4; } /* The tail is half-word aligned if we have count >= 2 */ if (count >= 2) { __raw_writew(c, to); to += 2; count -= 2; } /* And finally, one last byte.. */ if (count) { __raw_writeb(c, to); } mb(); }
void _memset_c_io(volatile void __iomem *to, unsigned long c, long count) { /* */ if (count > 0 && ((u64)to & 1)) { __raw_writeb(c, to); to++; count--; } /* */ if (count >= 2 && ((u64)to & 2)) { __raw_writew(c, to); to += 2; count -= 2; } /* */ if (count >= 4 && ((u64)to & 4)) { __raw_writel(c, to); to += 4; count -= 4; } /* */ count -= 8; if (count >= 0) { do { __raw_writeq(c, to); to += 8; count -= 8; } while (count >= 0); } count += 8; /* */ if (count >= 4) { __raw_writel(c, to); to += 4; count -= 4; } /* */ if (count >= 2) { __raw_writew(c, to); to += 2; count -= 2; } /* */ if (count) { __raw_writeb(c, to); } mb(); }
static int sibyte_shutdown(struct clock_event_device *evt) { unsigned int cpu = smp_processor_id(); void __iomem *cfg; cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); /* Stop the timer until we actually program a shot */ __raw_writeq(0, cfg); return 0; }
/** * octeon_i2c_read_sw - write an I2C core register. * @i2c: The struct octeon_i2c. * @eop_reg: Register selector. * * Returns the data. * * The I2C core registers are accessed indirectly via the SW_TWSI CSR. */ static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg) { u64 tmp; __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI); do { tmp = __raw_readq(i2c->twsi_base + SW_TWSI); } while ((tmp & SW_TWSI_V) != 0); return tmp & 0xFF; }
static int xicor_write(uint8_t addr, int b) { while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; __raw_writeq(addr, SMB_CSR(R_SMB_CMD)); __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA)); __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE, SMB_CSR(R_SMB_START)); while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY) ; if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) { /* Clear error bit by writing a 1 */ __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS)); return -1; } else { return 0; } }
static void ichxrom_write(struct map_info *map, map_word d, unsigned long ofs) { switch(map->bankwidth) { case 1: __raw_writeb(d.x[0], addr(map,ofs)); break; case 2: __raw_writew(d.x[0], addr(map,ofs)); break; case 4: __raw_writel(d.x[0], addr(map,ofs)); break; #if BITS_PER_LONG >= 64 case 8: __raw_writeq(d.x[0], addr(map,ofs)); break; #endif } mb(); }
static void dw8250_serial_outq(struct uart_port *p, int offset, int value) { struct dw8250_data *d = p->private_data; value &= 0xff; __raw_writeq(value, p->membase + (offset << p->regshift)); /* Read back to ensure register write ordering. */ __raw_readq(p->membase + (UART_LCR << p->regshift)); if (offset == UART_LCR && !d->uart_16550_compatible) dw8250_check_lcr(p, value); }
void bcm1480_time_init(void) { int cpu = smp_processor_id(); int irq = K_BCM1480_INT_TIMER_0+cpu; /* Only have 4 general purpose timers */ if (cpu > 3) { BUG(); } bcm1480_mask_irq(cpu, irq); /* Map the timer interrupt to ip[4] of this cpu */ __raw_writeq(IMR_IP4_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq<<3))); /* the general purpose timer ticks at 1 Mhz independent of the rest of the system */ /* Disable the timer and set up the count */ __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); __raw_writeq( BCM1480_HPT_VALUE/HZ , IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); /* Set the timer running */ __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); bcm1480_unmask_irq(cpu, irq); bcm1480_steal_irq(irq); /* * This interrupt is "special" in that it doesn't use the request_irq * way to hook the irq line. The timer interrupt is initialized early * enough to make this a major pain, and it's also firing enough to * warrant a bit of special case code. bcm1480_timer_interrupt is * called directly from irq_handler.S when IP[4] is set during an * interrupt */ }