void __s5p_cec_copy_packet(char *data, size_t count)
{
int i = 0;
u8 reg;
/* copy packet to hardware buffer */
while (i < count) {
writeb(data[i], cec_base + (CEC_TX_BUFF0 + (i*4)));
i++;
}
/* set number of bytes to transfer */
writeb(count, cec_base + CEC_TX_BYTES);
__s5p_cec_set_tx_state(STATE_TX);
/* start transfer */
reg = readb(cec_base + CEC_TX_CTRL);
reg |= CEC_TX_CTRL_START;
/* if message is broadcast message - set corresponding bit */
if ((data[0] & CEC_MESSAGE_BROADCAST_MASK) == CEC_MESSAGE_BROADCAST)
reg |= CEC_TX_CTRL_BCAST;
else
reg &= ~CEC_TX_CTRL_BCAST;
/* set number of retransmissions */
reg |= 0x50;
writeb(reg, cec_base + CEC_TX_CTRL);
}
/**
* @brief CEC interrupt handler
*
* Handles interrupt requests from CEC hardware. \n
* Action depends on current state of CEC hardware.
*/
irqreturn_t s5p_cec_irq_handler(int irq, void *dev_id)
{
u32 status = 0;
/* read flag register */
/* is this our interrupt? */
/*
if (!(flag & (1 << HDMI_IRQ_CEC))) {
return IRQ_NONE;
}
*/
status = __s5p_cec_get_status();
if (status & CEC_STATUS_TX_DONE) {
if (status & CEC_STATUS_TX_ERROR) {
CECIFPRINTK(" CEC_STATUS_TX_ERROR!\n");
__s5p_cec_set_tx_state(STATE_ERROR);
} else {
CECIFPRINTK(" CEC_STATUS_TX_DONE!\n");
__s5p_cec_set_tx_state(STATE_DONE);
}
__s5p_clr_pending_tx();
wake_up_interruptible(&cec_tx_struct.waitq);
}
if (status & CEC_STATUS_RX_DONE) {
if (status & CEC_STATUS_RX_ERROR) {
CECIFPRINTK(" CEC_STATUS_RX_ERROR!\n");
__s5p_cec_rx_reset();
} else {
u32 size;
CECIFPRINTK(" CEC_STATUS_RX_DONE!\n");
/* copy data from internal buffer */
size = status >> 24;
spin_lock(&cec_rx_struct.lock);
__s5p_cec_get_rx_buf(size, cec_rx_struct.buffer);
cec_rx_struct.size = size;
__s5p_cec_set_rx_state(STATE_DONE);
spin_unlock(&cec_rx_struct.lock);
__s5p_cec_enable_rx();
}
/* clear interrupt pending bit */
__s5p_clr_pending_rx();
wake_up_interruptible(&cec_rx_struct.waitq);
}
return IRQ_HANDLED;
}
