/** * \brief Initiates a write packet operation without sending a STOP condition when done * * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus * without sending a stop condition, thus retaining ownership of the bus when * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or * \ref i2c_master_write_packet_wait "write" with stop condition or sending * a stop with the \ref i2c_master_send_stop function must be performed. * * This is the non-blocking equivalent of \ref i2c_master_write_packet_wait_no_stop. * * \param[in,out] module Pointer to software module struct * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer * * \return Status of starting writing I<SUP>2</SUP>C packet job. * \retval STATUS_OK If writing was started successfully * \retval STATUS_BUSY If module is currently busy with another */ enum status_code i2c_master_write_packet_job_no_stop( struct i2c_master_module *const module, struct i2c_master_packet *const packet) { /* Sanity check */ Assert(module); Assert(module->hw); Assert(packet); /* Check if the I2C module is busy with another job. */ if (module->buffer_remaining > 0) { return STATUS_BUSY; } /* Do not send stop condition when done */ module->send_stop = false; /* Start write operation */ return _i2c_master_write_packet(module, packet); }
/** * \brief Writes data packet to slave without sending a stop condition when done * * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus * without sending a stop condition, thus retaining ownership of the bus when * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or * \ref i2c_master_write_packet_wait "write" with stop condition or sending a * stop with the \ref i2c_master_send_stop function must be performed. * * \note This will stall the device from any other operation. For * interrupt-driven operation, see \ref i2c_master_read_packet_job. * * \param[in,out] module Pointer to software module struct * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer * * \return Status of reading packet. * \retval STATUS_OK If packet was read * \retval STATUS_BUSY If master module is busy * \retval STATUS_ERR_DENIED If error on bus * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave * acknowledged the address * \retval STATUS_ERR_TIMEOUT If timeout occurred * \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent * data, indicating that slave do not want * more data */ enum status_code i2c_master_write_packet_wait_no_stop( struct i2c_master_module *const module, struct i2c_master_packet *const packet) { /* Sanity check */ Assert(module); Assert(module->hw); Assert(packet); #if I2C_MASTER_CALLBACK_MODE == true /* Check if the I2C module is busy with a job */ if (module->buffer_remaining > 0) { return STATUS_BUSY; } #endif module->send_stop = false; return _i2c_master_write_packet(module, packet); }
/** * \brief Initiates a write packet operation * * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C * bus. This is the non-blocking equivalent of \ref i2c_master_write_packet_wait. * * \param[in,out] module Pointer to software module struct * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer * * \return Status of starting writing I<SUP>2</SUP>C packet job. * \retval STATUS_OK If writing was started successfully * \retval STATUS_BUSY If module is currently busy with another transfer */ enum status_code i2c_master_write_packet_job( struct i2c_master_module *const module, struct i2c_master_packet *const packet) { /* Sanity check */ Assert(module); Assert(module->hw); Assert(packet); /* Check if the I2C module is busy with another job. */ if (module->buffer_remaining > 0) { return STATUS_BUSY; } /* Make sure we send STOP at end*/ module->send_stop = true; /* Start write operation */ return _i2c_master_write_packet(module, packet); }