/**
* Print program, with options.
*/
void
_mesa_fprint_program_opt(FILE *f,
const struct gl_program *prog,
gl_prog_print_mode mode,
GLboolean lineNumbers)
{
GLuint i, indent = 0;
switch (prog->Target) {
case GL_VERTEX_PROGRAM_ARB:
if (mode == PROG_PRINT_ARB)
fprintf(f, "!!ARBvp1.0\n");
else
fprintf(f, "# Vertex Program/Shader %u\n", prog->Id);
break;
case GL_FRAGMENT_PROGRAM_ARB:
if (mode == PROG_PRINT_ARB)
fprintf(f, "!!ARBfp1.0\n");
else
fprintf(f, "# Fragment Program/Shader %u\n", prog->Id);
break;
case GL_GEOMETRY_PROGRAM_NV:
fprintf(f, "# Geometry Shader\n");
}
for (i = 0; i < prog->NumInstructions; i++) {
if (lineNumbers)
fprintf(f, "%3d: ", i);
indent = _mesa_fprint_instruction_opt(f, prog->Instructions + i,
indent, mode, prog);
}
}
GLint
_mesa_print_instruction_opt(const struct prog_instruction *inst,
GLint indent,
gl_prog_print_mode mode,
const struct gl_program *prog)
{
return _mesa_fprint_instruction_opt(stderr, inst, indent, mode, prog);
}
void
dump_assembly(void *assembly, int num_annotations, struct annotation *annotation,
struct brw_context *brw, const struct gl_program *prog)
{
const char *last_annotation_string = NULL;
const void *last_annotation_ir = NULL;
for (int i = 0; i < num_annotations; i++) {
int start_offset = annotation[i].offset;
int end_offset = annotation[i + 1].offset;
if (annotation[i].block_start) {
fprintf(stderr, " START B%d", annotation[i].block_start->num);
foreach_list_typed(struct bblock_link, predecessor_link, link,
&annotation[i].block_start->parents) {
struct bblock_t *predecessor_block = predecessor_link->block;
fprintf(stderr, " <-B%d", predecessor_block->num);
}
fprintf(stderr, "\n");
}
if (last_annotation_ir != annotation[i].ir) {
last_annotation_ir = annotation[i].ir;
if (last_annotation_ir) {
fprintf(stderr, " ");
if (!prog->Instructions)
fprint_ir(stderr, annotation[i].ir);
else {
const struct prog_instruction *pi =
(const struct prog_instruction *)annotation[i].ir;
fprintf(stderr, "%d: ",
(int)(pi - prog->Instructions));
_mesa_fprint_instruction_opt(stderr,
pi,
0, PROG_PRINT_DEBUG, NULL);
}
fprintf(stderr, "\n");
}
}
if (last_annotation_string != annotation[i].annotation) {
last_annotation_string = annotation[i].annotation;
if (last_annotation_string)
fprintf(stderr, " %s\n", last_annotation_string);
}
brw_disassemble(brw, assembly, start_offset, end_offset, stderr);
if (annotation[i].block_end) {
fprintf(stderr, " END B%d", annotation[i].block_end->num);
foreach_list_typed(struct bblock_link, successor_link, link,
&annotation[i].block_end->children) {
struct bblock_t *successor_block = successor_link->block;
fprintf(stderr, " ->B%d", successor_block->num);
}
fprintf(stderr, "\n");
}
void
_mesa_print_instruction(const struct prog_instruction *inst)
{
/* note: 4th param should be ignored for PROG_PRINT_DEBUG */
_mesa_fprint_instruction_opt(stderr, inst, 0, PROG_PRINT_DEBUG, NULL);
}
void
vec4_generator::generate_code(exec_list *instructions)
{
int last_native_insn_offset = 0;
const char *last_annotation_string = NULL;
const void *last_annotation_ir = NULL;
if (unlikely(debug_flag)) {
if (shader_prog) {
fprintf(stderr, "Native code for %s vertex shader %d:\n",
shader_prog->Label ? shader_prog->Label : "unnamed",
shader_prog->Name);
} else {
fprintf(stderr, "Native code for vertex program %d:\n", prog->Id);
}
}
foreach_list(node, instructions) {
vec4_instruction *inst = (vec4_instruction *)node;
struct brw_reg src[3], dst;
if (unlikely(debug_flag)) {
if (last_annotation_ir != inst->ir) {
last_annotation_ir = inst->ir;
if (last_annotation_ir) {
fprintf(stderr, " ");
if (shader_prog) {
((ir_instruction *) last_annotation_ir)->fprint(stderr);
} else {
const prog_instruction *vpi;
vpi = (const prog_instruction *) inst->ir;
fprintf(stderr, "%d: ", (int)(vpi - prog->Instructions));
_mesa_fprint_instruction_opt(stderr, vpi, 0,
PROG_PRINT_DEBUG, NULL);
}
fprintf(stderr, "\n");
}
}
if (last_annotation_string != inst->annotation) {
last_annotation_string = inst->annotation;
if (last_annotation_string)
fprintf(stderr, " %s\n", last_annotation_string);
}
}
for (unsigned int i = 0; i < 3; i++) {
src[i] = inst->get_src(this->prog_data, i);
}
dst = inst->get_dst();
brw_set_conditionalmod(p, inst->conditional_mod);
brw_set_predicate_control(p, inst->predicate);
brw_set_predicate_inverse(p, inst->predicate_inverse);
brw_set_saturate(p, inst->saturate);
brw_set_mask_control(p, inst->force_writemask_all);
unsigned pre_emit_nr_insn = p->nr_insn;
generate_vec4_instruction(inst, dst, src);
if (inst->no_dd_clear || inst->no_dd_check) {
assert(p->nr_insn == pre_emit_nr_insn + 1 ||
!"no_dd_check or no_dd_clear set for IR emitting more "
"than 1 instruction");
struct brw_instruction *last = &p->store[pre_emit_nr_insn];
if (inst->no_dd_clear)
last->header.dependency_control |= BRW_DEPENDENCY_NOTCLEARED;
if (inst->no_dd_check)
last->header.dependency_control |= BRW_DEPENDENCY_NOTCHECKED;
}
if (unlikely(debug_flag)) {
brw_dump_compile(p, stderr,
last_native_insn_offset, p->next_insn_offset);
}
last_native_insn_offset = p->next_insn_offset;
}
void
gen8_vec4_generator::generate_code(exec_list *instructions)
{
int last_native_inst_offset = 0;
const char *last_annotation_string = NULL;
const void *last_annotation_ir = NULL;
if (unlikely(debug_flag)) {
if (shader_prog) {
printf("Native code for vertex shader %d:\n", shader_prog->Name);
} else {
printf("Native code for vertex program %d:\n", prog->Id);
}
}
foreach_list(node, instructions) {
vec4_instruction *ir = (vec4_instruction *) node;
struct brw_reg src[3], dst;
if (unlikely(debug_flag)) {
if (last_annotation_ir != ir->ir) {
last_annotation_ir = ir->ir;
if (last_annotation_ir) {
printf(" ");
if (shader_prog) {
((ir_instruction *) last_annotation_ir)->print();
} else {
const prog_instruction *vpi;
vpi = (const prog_instruction *) ir->ir;
printf("%d: ", (int)(vpi - prog->Instructions));
_mesa_fprint_instruction_opt(stdout, vpi, 0,
PROG_PRINT_DEBUG, NULL);
}
printf("\n");
}
}
if (last_annotation_string != ir->annotation) {
last_annotation_string = ir->annotation;
if (last_annotation_string)
printf(" %s\n", last_annotation_string);
}
}
for (unsigned int i = 0; i < 3; i++) {
src[i] = ir->get_src(prog_data, i);
}
dst = ir->get_dst();
default_state.conditional_mod = ir->conditional_mod;
default_state.predicate = ir->predicate;
default_state.predicate_inverse = ir->predicate_inverse;
default_state.saturate = ir->saturate;
const unsigned pre_emit_nr_inst = nr_inst;
generate_vec4_instruction(ir, dst, src);
if (ir->no_dd_clear || ir->no_dd_check) {
assert(nr_inst == pre_emit_nr_inst + 1 ||
!"no_dd_check or no_dd_clear set for IR emitting more "
"than 1 instruction");
gen8_instruction *last = &store[pre_emit_nr_inst];
gen8_set_no_dd_clear(last, ir->no_dd_clear);
gen8_set_no_dd_check(last, ir->no_dd_check);
}
if (unlikely(debug_flag)) {
disassemble(stdout, last_native_inst_offset, next_inst_offset);
}
last_native_inst_offset = next_inst_offset;
}
void
vec4_generator::generate_code(exec_list *instructions)
{
int last_native_insn_offset = 0;
const char *last_annotation_string = NULL;
const void *last_annotation_ir = NULL;
if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
if (shader) {
printf("Native code for vertex shader %d:\n", prog->Name);
} else {
printf("Native code for vertex program %d:\n", c->vp->program.Base.Id);
}
}
foreach_list(node, instructions) {
vec4_instruction *inst = (vec4_instruction *)node;
struct brw_reg src[3], dst;
if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
if (last_annotation_ir != inst->ir) {
last_annotation_ir = inst->ir;
if (last_annotation_ir) {
printf(" ");
if (shader) {
((ir_instruction *) last_annotation_ir)->print();
} else {
const prog_instruction *vpi;
vpi = (const prog_instruction *) inst->ir;
printf("%d: ", (int)(vpi - vp->Base.Instructions));
_mesa_fprint_instruction_opt(stdout, vpi, 0,
PROG_PRINT_DEBUG, NULL);
}
printf("\n");
}
}
if (last_annotation_string != inst->annotation) {
last_annotation_string = inst->annotation;
if (last_annotation_string)
printf(" %s\n", last_annotation_string);
}
}
for (unsigned int i = 0; i < 3; i++) {
src[i] = inst->get_src(i);
}
dst = inst->get_dst();
brw_set_conditionalmod(p, inst->conditional_mod);
brw_set_predicate_control(p, inst->predicate);
brw_set_predicate_inverse(p, inst->predicate_inverse);
brw_set_saturate(p, inst->saturate);
switch (inst->opcode) {
case BRW_OPCODE_MOV:
brw_MOV(p, dst, src[0]);
break;
case BRW_OPCODE_ADD:
brw_ADD(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_MUL:
brw_MUL(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_MACH:
brw_set_acc_write_control(p, 1);
brw_MACH(p, dst, src[0], src[1]);
brw_set_acc_write_control(p, 0);
break;
case BRW_OPCODE_FRC:
brw_FRC(p, dst, src[0]);
break;
case BRW_OPCODE_RNDD:
brw_RNDD(p, dst, src[0]);
break;
case BRW_OPCODE_RNDE:
brw_RNDE(p, dst, src[0]);
break;
case BRW_OPCODE_RNDZ:
brw_RNDZ(p, dst, src[0]);
break;
case BRW_OPCODE_AND:
brw_AND(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_OR:
brw_OR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_XOR:
brw_XOR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_NOT:
brw_NOT(p, dst, src[0]);
break;
case BRW_OPCODE_ASR:
brw_ASR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_SHR:
brw_SHR(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_SHL:
brw_SHL(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_CMP:
brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
break;
case BRW_OPCODE_SEL:
brw_SEL(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_DPH:
brw_DPH(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_DP4:
brw_DP4(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_DP3:
brw_DP3(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_DP2:
brw_DP2(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_IF:
if (inst->src[0].file != BAD_FILE) {
/* The instruction has an embedded compare (only allowed on gen6) */
assert(intel->gen == 6);
gen6_IF(p, inst->conditional_mod, src[0], src[1]);
} else {
struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
brw_inst->header.predicate_control = inst->predicate;
}
break;
case BRW_OPCODE_ELSE:
brw_ELSE(p);
break;
case BRW_OPCODE_ENDIF:
brw_ENDIF(p);
break;
case BRW_OPCODE_DO:
brw_DO(p, BRW_EXECUTE_8);
break;
case BRW_OPCODE_BREAK:
brw_BREAK(p);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
break;
case BRW_OPCODE_CONTINUE:
/* FINISHME: We need to write the loop instruction support still. */
if (intel->gen >= 6)
gen6_CONT(p);
else
brw_CONT(p);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
break;
case BRW_OPCODE_WHILE:
brw_WHILE(p);
break;
default:
generate_vs_instruction(inst, dst, src);
break;
}
if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
brw_dump_compile(p, stdout,
last_native_insn_offset, p->next_insn_offset);
}
last_native_insn_offset = p->next_insn_offset;
}
