__m256i test_mm256_sad_epu8(__m256i x, __m256i y) {
// CHECK-LABEL: test_mm256_sad_epu8
// CHECK: call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %{{.*}}, <32 x i8> %{{.*}})
return _mm256_sad_epu8(x, y);
}
void aom_sad64x64x4d_avx2(const uint8_t *src, int src_stride,
const uint8_t *const ref[4], int ref_stride,
uint32_t res[4]) {
__m256i src_reg, srcnext_reg, ref0_reg, ref0next_reg;
__m256i ref1_reg, ref1next_reg, ref2_reg, ref2next_reg;
__m256i ref3_reg, ref3next_reg;
__m256i sum_ref0, sum_ref1, sum_ref2, sum_ref3;
__m256i sum_mlow, sum_mhigh;
int i;
const uint8_t *ref0, *ref1, *ref2, *ref3;
ref0 = ref[0];
ref1 = ref[1];
ref2 = ref[2];
ref3 = ref[3];
sum_ref0 = _mm256_set1_epi16(0);
sum_ref1 = _mm256_set1_epi16(0);
sum_ref2 = _mm256_set1_epi16(0);
sum_ref3 = _mm256_set1_epi16(0);
for (i = 0; i < 64; i++) {
// load 64 bytes from src and all refs
src_reg = _mm256_loadu_si256((const __m256i *)src);
srcnext_reg = _mm256_loadu_si256((const __m256i *)(src + 32));
ref0_reg = _mm256_loadu_si256((const __m256i *)ref0);
ref0next_reg = _mm256_loadu_si256((const __m256i *)(ref0 + 32));
ref1_reg = _mm256_loadu_si256((const __m256i *)ref1);
ref1next_reg = _mm256_loadu_si256((const __m256i *)(ref1 + 32));
ref2_reg = _mm256_loadu_si256((const __m256i *)ref2);
ref2next_reg = _mm256_loadu_si256((const __m256i *)(ref2 + 32));
ref3_reg = _mm256_loadu_si256((const __m256i *)ref3);
ref3next_reg = _mm256_loadu_si256((const __m256i *)(ref3 + 32));
// sum of the absolute differences between every ref-i to src
ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
ref3_reg = _mm256_sad_epu8(ref3_reg, src_reg);
ref0next_reg = _mm256_sad_epu8(ref0next_reg, srcnext_reg);
ref1next_reg = _mm256_sad_epu8(ref1next_reg, srcnext_reg);
ref2next_reg = _mm256_sad_epu8(ref2next_reg, srcnext_reg);
ref3next_reg = _mm256_sad_epu8(ref3next_reg, srcnext_reg);
// sum every ref-i
sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
sum_ref3 = _mm256_add_epi32(sum_ref3, ref3_reg);
sum_ref0 = _mm256_add_epi32(sum_ref0, ref0next_reg);
sum_ref1 = _mm256_add_epi32(sum_ref1, ref1next_reg);
sum_ref2 = _mm256_add_epi32(sum_ref2, ref2next_reg);
sum_ref3 = _mm256_add_epi32(sum_ref3, ref3next_reg);
src += src_stride;
ref0 += ref_stride;
ref1 += ref_stride;
ref2 += ref_stride;
ref3 += ref_stride;
}
{
__m128i sum;
// in sum_ref-i the result is saved in the first 4 bytes
// the other 4 bytes are zeroed.
// sum_ref1 and sum_ref3 are shifted left by 4 bytes
sum_ref1 = _mm256_slli_si256(sum_ref1, 4);
sum_ref3 = _mm256_slli_si256(sum_ref3, 4);
// merge sum_ref0 and sum_ref1 also sum_ref2 and sum_ref3
sum_ref0 = _mm256_or_si256(sum_ref0, sum_ref1);
sum_ref2 = _mm256_or_si256(sum_ref2, sum_ref3);
// merge every 64 bit from each sum_ref-i
sum_mlow = _mm256_unpacklo_epi64(sum_ref0, sum_ref2);
sum_mhigh = _mm256_unpackhi_epi64(sum_ref0, sum_ref2);
// add the low 64 bit to the high 64 bit
sum_mlow = _mm256_add_epi32(sum_mlow, sum_mhigh);
// add the low 128 bit to the high 128 bit
sum = _mm_add_epi32(_mm256_castsi256_si128(sum_mlow),
_mm256_extractf128_si256(sum_mlow, 1));
_mm_storeu_si128((__m128i *)(res), sum);
}
_mm256_zeroupper();
}
void extern
avx2_test (void)
{
x = _mm256_sad_epu8 (x, x);
}
__m256i test_mm256_sad_epu8(__m256i x, __m256i y) {
// CHECK: @llvm.x86.avx2.psad.bw
return _mm256_sad_epu8(x, y);
}
// count genotype sum and number of calls, not requiring 16-aligned p
COREARRAY_DLL_DEFAULT C_UInt8* vec_u8_geno_count(C_UInt8 *p,
size_t n, C_Int32 &out_sum, C_Int32 &out_num)
{
C_Int32 sum=0, num=0;
#if defined(COREARRAY_SIMD_AVX2)
const __m256i three = _mm256_set1_epi8(3);
const __m256i zero = _mm256_setzero_si256();
__m256i sum32 = zero, num32 = zero;
size_t limit_by_U8 = 0;
for (; n >= 32; )
{
__m256i v = _mm256_loadu_si256((__m256i const*)p);
p += 32;
__m256i m = _mm256_cmpgt_epi8(three, _mm256_min_epu8(v, three));
sum32 = _mm256_add_epi8(sum32, _mm256_and_si256(v, m));
num32 = _mm256_sub_epi8(num32, m);
n -= 32;
limit_by_U8 ++;
if ((limit_by_U8 >= 127) || (n < 32))
{
// add to sum
sum32 = _mm256_sad_epu8(sum32, zero);
sum32 = _mm256_add_epi32(sum32,
_mm256_permute4x64_epi64(sum32, _MM_SHUFFLE(1,0,3,2)));
sum32 = _mm256_add_epi32(sum32,
_mm256_permute4x64_epi64(sum32, _MM_SHUFFLE(0,0,0,1)));
sum += _mm_cvtsi128_si32(_mm256_castsi256_si128(sum32));
// add to num
num32 = _mm256_sad_epu8(num32, zero);
num32 = _mm256_add_epi32(num32,
_mm256_permute4x64_epi64(num32, _MM_SHUFFLE(1,0,3,2)));
num32 = _mm256_add_epi32(num32,
_mm256_permute4x64_epi64(num32, _MM_SHUFFLE(0,0,0,1)));
num += _mm_cvtsi128_si32(_mm256_castsi256_si128(num32));
// reset
sum32 = num32 = zero;
limit_by_U8 = 0;
}
}
#elif defined(COREARRAY_SIMD_SSE2)
// header, 16-byte aligned
size_t h = (16 - ((size_t)p & 0x0F)) & 0x0F;
for (; (n > 0) && (h > 0); n--, h--, p++)
if (*p <= 2) { sum += *p; num++; }
const __m128i three = _mm_set1_epi8(3);
const __m128i zero = _mm_setzero_si128();
__m128i sum16=zero, num16=zero;
size_t limit_by_U8 = 0;
for (; n >= 16; )
{
__m128i v = _mm_load_si128((__m128i const*)p);
p += 16;
__m128i m = _mm_cmpgt_epi8(three, _mm_min_epu8(v, three));
sum16 = _mm_add_epi8(sum16, v & m);
num16 = _mm_sub_epi8(num16, m);
n -= 16;
limit_by_U8 ++;
if ((limit_by_U8 >= 127) || (n < 16))
{
// add to sum
sum16 = _mm_sad_epu8(sum16, zero);
sum += _mm_cvtsi128_si32(sum16);
sum += _mm_cvtsi128_si32(_mm_shuffle_epi32(sum16, 2));
// add to num
num16 = _mm_sad_epu8(num16, zero);
num += _mm_cvtsi128_si32(num16);
num += _mm_cvtsi128_si32(_mm_shuffle_epi32(num16, 2));
// reset
sum16 = num16 = zero;
limit_by_U8 = 0;
}
}
#endif
for (; n > 0; n--, p++)
if (*p <= 2) { sum += *p; num++; }
out_sum = sum;
out_num = num;
return p;
}
