/********
* MAIN *
********/
void main()
{
#ifdef SIMULATOR
struct ip_addr dump_ipaddr, dump_netmask, dump_gw;
#else
struct ip_addr eth_ipaddr, eth_netmask, eth_gw;
#endif
struct ip_addr ipsec_ipaddr, ipsec_netmask, ipsec_gw;
unsigned int i;
serinit(); /* init serial port */
printf("lwIP - IPsec Dynamic SAD/SPD configuration demo (compiled %s at %s)\n", __DATE__, __TIME__);
printf("CVS ID: $Id: main.c,v 1.8 2003/12/12 14:36:33 schec2 Exp $\n\n");
/* initialize lwIP */
etharp_init();
mem_init();
memp_init();
pbuf_init();
netif_init();
ip_init();
udp_init();
tcp_init();
printf("TCP/IP initialized.\n");
#ifdef SIMULATOR
/* configure dummy device */
IP4_ADDR(&dump_ipaddr, 192,168,1,3);
IP4_ADDR(&dump_netmask, 255,255,255,0);
IP4_ADDR(&dump_gw, 192,168,1,1);
/* configure IPsec device */
IP4_ADDR(&ipsec_ipaddr, 192,168,1,3);
IP4_ADDR(&ipsec_netmask, 255,255,255,0);
IP4_ADDR(&ipsec_gw, 192,168,1,1);
#endif
#ifdef MCB167NET
/* configure Ethernet device */
IP4_ADDR(ð_ipaddr, 192,168,1,3);
IP4_ADDR(ð_netmask, 255,255,255,0);
IP4_ADDR(ð_gw, 192,168,1,1);
/* configure IPsec device */
IP4_ADDR(&ipsec_ipaddr, 192,168,1,3);
IP4_ADDR(&ipsec_netmask, 255,255,255,0);
IP4_ADDR(&ipsec_gw, 192,168,1,1);
#endif
#ifdef PHYCORE167HSE
/* configure Ethernet device */
IP4_ADDR(ð_ipaddr, 192,168,1,4);
IP4_ADDR(ð_netmask, 255,255,255,0);
IP4_ADDR(ð_gw, 192,168,1,1);
/* configure IPsec device */
IP4_ADDR(&ipsec_ipaddr, 192,168,1,4);
IP4_ADDR(&ipsec_netmask, 255,255,255,0);
IP4_ADDR(&ipsec_gw, 192,168,1,1);
#endif
/* Initialize the physical device first (so that ethif->next will point *
* to ipsecif). The IPsec device will process the packets and pass them *
* upper to the IP layer (using ip_input) *
* If the simulator is used, dumpdev will replace cs8900. */
#ifdef SIMULATOR
printf("Setting up dp0...");
dumpif = netif_add(&dump_ipaddr, &dump_netmask, &dump_gw, NULL, dumpdev_init, ipsecdev_input);
printf("OK\n");
printf("Setting up is0...");
ipsecif = netif_add(&ipsec_ipaddr, &ipsec_netmask, &ipsec_gw, NULL, ipsecdev_init, ip_input);
printf("OK\n");
#else
printf("Setting up et0...");
ethif = netif_add(ð_ipaddr, ð_netmask, ð_gw, NULL, cs8900if_init, ipsecdev_input);
printf("OK\n");
printf("Setting up is0...");
ipsecif = netif_add(&ipsec_ipaddr, &ipsec_netmask, &ipsec_gw, NULL, ipsecdev_init, ip_input);
printf("OK\n");
#endif
/* configure IPsec tunnel */
#ifdef PHYCORE167HSE
ipsec_set_tunnel("192.168.1.4", "192.168.1.5");
#else
ipsec_set_tunnel("192.168.1.3", "192.168.1.5");
#endif
/* set the IPsec interface "is0" as default interface for lwIP */
netif_set_default(ipsecif); /* use ipsec interface by default */
/* start custom applications here */
dumpwebpage_init(); /* start dumpwebpage */
netconfig_init(); /* start dynamic network confiuratio*/
printf("Applications started.\n");
DP2 = 0x00FF; /* configure the status LED on Port2*/
ODP2 = 0x0000;
while(1)
{
P2 = ~P2; /* blink LED */
for (i = 0; i < 50000; i++)
{
_nop_(); _nop_(); /* delay or use this time for the */
_nop_(); _nop_(); /* application */
_nop_(); _nop_();
if((i % 250) == 0)
{ /* periodically call to the */
#ifdef SIMULATOR
dumpdev_service(dumpif);/* dump device driver (polling mode)*/
#else
cs8900if_service(ethif);/* CS8900 driver (polling mode) */
#endif
tcp_tmr(); /* poll TCP timer */
}
}
}
}
void main (void) {
unsigned int i;
P0_DIR |= 0x02; // P0.1 (RxD) is an input
P0_ALT |= 0x06; // Select alternate functions on pins P0.1 and P0.2
T2CON = 0x34; /* Use Timer 2 as baudrate generator */
RCAP2H = 0xFF;
RCAP2L = 0xF7; /* 57600 baud @ 16MHz */
SCON = 0x50; /* enable serial uart & receiver */
EA = 1; /* Enable global interrupt flag */
//TestSerial (); // uncomment this function to verify serial communication
#if 0 // init ISD51 and start user program until the uVision2 Debugger connects
ISDinit (); // initialize uVision2 Debugger and continue program run
#endif
#if 0 // init ISD51 and wait until the uVision2 Debugger connects
ISDwait (); // wait for connection to uVision2 Debugger
#endif
for (i = 0; i < sizeof (testarray); i++) {
j = testarray[i];
}
while (1) {
#if 1 // init ISD51 only when the uVision2 Debugger tries to connect
ISDcheck(); // initialize uVision2 Debugger and continue program run
#endif
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
#if 0 // you may use ISDbreak when ISD51 is started with ISDcheck or ISDwait
ISDbreak (); // hard coded stop (breakpoint)
#endif
delay();
_nop_();
_nop_();
_nop_();
}
}
void Delay_5us(void)
{
_nop_();_nop_();_nop_();_nop_();
_nop_();_nop_();_nop_();_nop_();
_nop_();_nop_();_nop_();_nop_();
_nop_();_nop_();_nop_();_nop_();
_nop_();_nop_();_nop_();_nop_();
_nop_();_nop_();_nop_();_nop_();
}
void delay()
{
_nop_();_nop_();_nop_();_nop_();_nop_();
}
void SendCOMMSlinkChar(void) {
#pragma asm
EXTRN BIT (sendRequestCurrentBit)
EXTRN DATA (sendRequestSequence)
EXTRN DATA (sendRequestCmd)
EXTRN DATA (debug_array_2)
;XRL P0,#80H //toggle pin
;MOV A,P0
;ANL A,#80H
;JZ PIN_IS_ZERO
;MOV TH0,#0xFF
;MOV TL0,#0xCD
;RET
;PIN_IS_ZERO: MOV TH0,#0xFE
;MOV TL0,#0x0B
;
;
MOV A,sendRequestSequence
JB ACC.0,CHECK_FOR_LAST_SEQ
;
JNZ CHECK_FOR_STOP_BIT
MOV debug_array_2,TL0
WE_ARE_STARTING_ONE: SETB sendRequestCurrentBit
MOV TH0,#0xF3
MOV TL0,#0xC0
JMP P07_PIN_UP
;
CHECK_FOR_STOP_BIT: CJNE A,#18,SWAP_THE_CMD
WE_ARE_STARTING_ZERO: CLR sendRequestCurrentBit
MOV TH0,#0xFF
MOV TL0,#0xCD
JMP P07_PIN_UP
;
SWAP_THE_CMD: MOV A,sendRequestCmd
RL A
MOV sendRequestCmd,A
JB ACC.0,WE_ARE_STARTING_ONE
JMP WE_ARE_STARTING_ZERO
;
;
P07_PIN_UP: ;ORL P0,#0x80
#pragma endasm
_nop_ ();
#pragma asm
JMP EXIT_ISR
;
;
CHECK_FOR_LAST_SEQ: MOV A,sendRequestSequence
CJNE A,#19,ZERO_PIN_STATE
CLR TR0
#pragma endasm
_nop_ ();
_nop_ ();
_nop_ ();
_nop_ ();
_nop_ ();
_nop_ ();
_nop_ ();
_nop_ ();
#pragma asm
;ANL P0MDOUT,#0x7F
;MOV SFRPAGE,#01H
;ORL 0x54,#01H
;ORL 0x58,#01H
;MOV P1,0x58
;MOV P1DIR,0x54
;ANL P0,#0x7F
RET
;
;
ZERO_PIN_STATE: JB sendRequestCurrentBit, WE_ARE_STOPPING_ONE
MOV TH0,#0xF3
MOV TL0,#0xC0
JMP P10_PIN_DOWN
;
WE_ARE_STOPPING_ONE: MOV TH0,#0xFF
MOV TL0,#0xCD
P10_PIN_DOWN: ;ANL P0,#0x7F
#pragma endasm
_nop_ ();
#pragma asm
;
;
EXIT_ISR: INC sendRequestSequence
#pragma endasm
}
BOOL DR_VendorCmnd(void)
{
WORD value;
WORD len,ind, bc; // xdata used here to conserve data ram; if not EEPROM writes don't work anymore
/*
union {
unsigned short ushort;
unsigned msb,lsb;
unsigned bytes[2]; // big endian, bytes[0] is MSB as far as C51 is concerned
} length;
*/
WORD i;
char *dscrRAM;
unsigned char xdata JTAGdata[400];
switch (SETUPDAT[1]){
case VR_ENABLE_AE_IN: // enable IN transfers
{
startMonitor();
break; // handshake phase triggered below
}
case VR_DISABLE_AE_IN: // disable IN transfers
{
stopMonitor();
break;
}
case VR_RESET_FIFOS: // reset in and out fifo
{
SYNCDELAY;
EP6FIFOCFG = 0x00; //0000_0000 disable auto-in
SYNCDELAY;
FIFORESET = 0x80;
SYNCDELAY;
FIFORESET = 0x06;
SYNCDELAY;
FIFORESET = 0x00;
SYNCDELAY;
EP6FIFOCFG = 0x08 ; //0000_1000 reenable auto-in
break;
}
case VR_DOWNLOAD_CPLD_CODE:
{
if (SETUPDAT[0]==VR_DOWNLOAD) {
if (JTAGinit)
{
IOC=0x00;
OEC = 0xBD; // configure TDO (bit 6) and TSmaster as input : 1011_1101
xsvfInitialize();
JTAGinit=FALSE;
}
len = SETUPDAT[6];
len |= SETUPDAT[7] << 8;
if (len>400)
{
xsvfReturn=10;
OEC = 0x0D; // configure JTAG pins to float : 0000_1111
JTAGinit=TRUE;
break;
}
value=0;
resetReadCounter(JTAGdata);
while(len) // Move new data through EP0OUT
{ // one packet at a time.
// Arm endpoint - do it here to clear (after sud avail)
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
while(EP0CS & bmEPBUSY);
bc = EP0BCL; // Get the new bytecount
for(i=0; i<bc; i++)
JTAGdata[value+i] = EP0BUF[i];
value += bc;
len -= bc;
}
if (SETUPDAT[2]==0x00) //complete
{
OEC = 0x0D; // configure JTAG pins to float : 0000_1111
JTAGinit=TRUE;
} else
{
xsvfReturn=xsvfRun();
if (xsvfReturn>0) // returns true if error
{
OEC = 0x0D; // configure JTAG pins to float : 0000_1101
JTAGinit=TRUE;
// return TRUE;
}
}
/* EP0BUF[0] = SETUPDAT[1];
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
return(FALSE); */
break;
}
else //case VR_XSVF_ERROR_CODE:
{
EP0BUF[0] = SETUPDAT[1];
EP0BUF[1]= xsvfReturn;
EP0BCH = 0;
EP0BCL = 2;
EP0CS |= bmHSNAK;
return(FALSE);
}
}
case VR_SET_DEVICE_NAME:
{
*EP0BUF = SETUPDAT[1];
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
while(EP0CS & bmEPBUSY); //wait for the data packet to arrive
dscrRAM = (char*)EZUSB_GetStringDscr(3); // get address of serial number descriptor-string in RAM
if (EP0BCL > MAX_NAME_LENGTH)
{
len=MAX_NAME_LENGTH;
} else
{
len=EP0BCL;
}
for (i=0;i<len;i++)
{
EEPROMWriteBYTE(STRING_ADDRESS+i, EP0BUF[i]); // write string to EEPROM
dscrRAM[2+i*2] = EP0BUF[i]; // write string to RAM
}
for (i=len; i<MAX_NAME_LENGTH; i++) // fill the rest with stop characters
{
EEPROMWriteBYTE(STRING_ADDRESS+i, ' '); // write string to EEPROM
dscrRAM[2+i*2] = ' '; // write string to RAM
}
EP0BCH = 0;
EP0BCL = 0;
return(FALSE);
}
case VR_RESETTIMESTAMPS:
{
tsReset=1; // RESET_TS=1; // assert RESET_TS pin for one instruction cycle (four clock cycles)
tsReset=0; // RESET_TS=0;
break;
}
case VR_CONFIG: // write bytes to SPI interface
case VR_EEPROM_BIASGEN_BYTES: // falls through and actual command is tested below
{
// the value bytes are the specific config command
// the index bytes are the arguments
// more data comes in the setupdat
SYNCDELAY;
value = SETUPDAT[2]; // Get request value
value |= SETUPDAT[3] << 8; // data comes little endian
ind = SETUPDAT[4]; // Get index
ind |= SETUPDAT[5] << 8;
len = SETUPDAT[6]; // length for data phase
len |= SETUPDAT[7] << 8;
switch(value&0xFF){ // take LSB for specific setup command because equalizer uses MSB for channel
// final short CMD_IPOT = 1, CMD_RESET_EQUALIZER = 2, CMD_SCANNER = 3, CMD_EQUALIZER = 4, CMD_SETBIT = 5, CMD_VDAC = 6;
#define CMD_IPOT 1
#define CMD_RESET_EQUALIZER 2
#define CMD_SCANNER 3
#define CMD_EQUALIZER 4
#define CMD_SETBIT 5
#define CMD_VDAC 6
#define CMD_INITDAC 7
case CMD_IPOT:
selectIPots;
numBiasBytes=len;
while(len){ // Move new data through EP0OUT, one packet at a time,
// eventually will get len down to zero by bc=64,64,15 (for example)
// Arm endpoint - do it here to clear (after sud avail)
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
SYNCDELAY;
while(EP0CS & bmEPBUSY); // spin here until data arrives
bc = EP0BCL; // Get the new bytecount
for(i=0; i<bc; i++){
sendConfigByte(EP0BUF[i]);
}
// value += bc; // inc eeprom value to write to, in case that's what we're doing
len -= bc; // dec total byte count
}
toggleLatch();
selectNone;
LED=!LED;
break;
case CMD_VDAC:
// EP0BUF has b0=channel (same for each DAC), b1=DAC1 MSB, b2=DAC1 LSB, b3=DAC0 MSB, b4=DAC0 LSB
if(len!=6) return TRUE; // error, should have 6 bytes which are just written out to DACs surrounded by dacNSync=0
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
SYNCDELAY;
while(EP0CS & bmEPBUSY); // spin here until data arrives
startDACSync();
for(i=0;i<6;i++){
sendDACByte(EP0BUF[i]);
}
endDACSync();
//toggleLDAC();
LED=!LED;
break;
case CMD_INITDAC:
initDAC();
LED=!LED;
break;
case CMD_SETBIT:
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
SYNCDELAY;
while(EP0CS & bmEPBUSY); // spin here until data arrives
// sends value=CMD_SETBIT, index=portbit with (port(b=0,d=1,e=2)<<8)|bitmask(e.g. 00001000) in MSB/LSB, byte[0]=value (1,0)
// also if button is tristable type in GUI, then byte[0] has tristate in bit1
{
bit bitval=(EP0BUF[0]&1); // 1=set, 0=clear
bit tristate=(EP0BUF[0]&2?1:0); // 1=tristate, 0=drive
unsigned char bitmask=SETUPDAT[4]; // bitmaskit mask, LSB of ind
switch(SETUPDAT[5]){ // this is port, MSB of ind
case 0: // port c
if(bitval) IOC|=bitmask; else IOC&= ~bitmask;
if(tristate) OEC&= ~bitmask; else OEC|=bitmask;
break;
case 1: // port d
if(bitval) IOD|=bitmask; else IOD&= ~bitmask;
if(tristate) OED&= ~bitmask; else OED|=bitmask;
break;
case 2: // port e
if(bitval) IOE|=bitmask; else IOE&= ~bitmask;
if(tristate) OEE&= ~bitmask; else OEE|=bitmask;
break;
default:
return TRUE; // error
}
LED=!LED;
}
break;
case CMD_SCANNER:
// index=1, continuous, index=0 go to channel
// Arm endpoint - do it here to clear (after sud avail) and get the data for channel to scan to if there is one. in any case must read data
// or subsequent requests will fail.
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
SYNCDELAY;
while(EP0CS & bmEPBUSY); // spin here until data arrives
if(ind==0){ // go to channel
ET2=0; // disable timer2 interrupt - IE.5
TR2=0; // stop timer2
i=255; // timeout on scanner clear
while(IOE&ScanSync && i-->0){ // clock scanner to end and timeout if there is no chip there
scanClock=1; // sync happens on falling edge
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
scanClock=0;
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
}
if(i==0) return TRUE; // scan to start failed
bc = EP0BUF[0]; // Get the channel number to scan to
for(i=0; i<bc; i++){
scanClock=1; _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
scanClock=0; _nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
}
}else{ // continuous scanning
RCAP2L=0xff-EP0BUF[0]; // load timer 2 low byte reload register with 0xff-period. period=0 reload is 0xff00 (255 counts), period=255, reload is 0x0000, period=64k
ET2=1; // enable timer2 interrupt - this is IE.5 bit addressable
TR2=1; // run timer2
}
LED=!LED;
break;
case CMD_EQUALIZER:
/*
the scheme right now for loading the AERKillBit and the local Vq's go as follows,
start with AddSel, which has 7 bits, RX0 to RX6, toggle bitlatch low/high - this signal
latches the bits for the decoder.
The output of the decoder is not activated till DataSel is chosen, the 10 bits are loaded, 5 bits
for Vq of SOS and 5bits for Iq of bpf, then when bitlatch is toggled low/high, then the
output of the decoder is released.
During this toggle of latch, the selected channel will also latch in the value on AERKillBit.
The only thing that I'm worrying about right now is that this value has to be remembered somewhere,
i.e. if I choose channels 10, 15 neurons to be inactivated, then even if I choose
new values for Vq and Iq, this information has to be stored somewhere. The
AERKillBit in essence is like an additional bit to the bits for the DataSel.
*/
// value has cmd in LSB, channel in MSB
// index has b11=bpfkilled, b10=lpfkilled, b9-5=qbpf, b4-0=qsos
/*All other 16-bit and 32-bit values are stored, contrary to other Intel
processors, in big endian format, with the high-order byte stored first. For
example, the LJMP and LCALL instructions expect 16-bit addresses that are
in big endian format.
*/
// index is channel address, bytes={gain,quality,killed (1=killed,0=active)}
selectAddr;
sendConfigBits(SETUPDAT[3],7); // send 7 bit address
toggleLatch();
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
selectNone;
_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();_nop_();
selectData;
sendConfigBits(SETUPDAT[4]&0x1f,5); // what is this for?
sendConfigBits((SETUPDAT[4]>>5)|(SETUPDAT[5]<<3),5);
/* commented out because of bug in cochleaams1b where select of a single kill bit is inverted so everybody but the one you want
is selected. however, the equalizer DAC current splitters still work
// set each killbit
selectLPFKill; // clears ybit
if(SETUPDAT[5]&4){ // kill LPF
aerKillBit=0; // hack
}else{
aerKillBit=0;
}
toggleLatch();
selectBPFKill; // sets ybit
if(SETUPDAT[5]&8){ // kill BPF
aerKillBit=0; // hack
}else{
aerKillBit=0;
}
*/
toggleLatch();
selectNone;
LED=!LED;
break;
case CMD_RESET_EQUALIZER:
return TRUE; // not yet implmented
LED=!LED;
break;
default:
return(TRUE); // don't recognize command
}
EP0BCH = 0;
EP0BCL = 0; // Arm endpoint with 0 byte to transfer
return(FALSE); // very important, otherwise get stall
}
case VR_SET_POWERDOWN: // control powerDown output bit
{
if (SETUPDAT[2])
{
powerDown=1;
} else
{
powerDown=0;
}
*EP0BUF=VR_SET_POWERDOWN;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with 1 byte to transfer
SYNCDELAY;
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break; // very important, otherwise get stall
}
/*
case VR_SETARRAYRESET: // set array reset, based on lsb of argument
{
if (SETUPDAT[2]&0x01)
{
IOE=IOE|ARRAY_RESET_MASK; //IOE|=arrayReset;
} else
{
IOE=IOE&NOT_ARRAY_RESET_MASK;
}
*EP0BUF=VR_SETARRAYRESET;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with 1 byte to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
return(FALSE); // very important, otherwise get stall
}
case VR_DOARRAYRESET: // reset array for fixed reset time
{
IOE=IOE&NOT_ARRAY_RESET_MASK;
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_(); // a few us
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
IOE=IOE|ARRAY_RESET_MASK; //IOE|=arrayReset;
*EP0BUF=VR_DOARRAYRESET;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with 1 byte to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
return (FALSE); // very important, otherwise get stall
}
*/
/* case VR_TIMESTAMP_TICK:
{
if (SETUPDAT[0]==VR_UPLOAD) //1010_0000 :vendor request to device, direction IN
{
EP0BUF[0] = SETUPDAT[1];
EP0BUF[1]= operationMode;
EP0BCH = 0;
EP0BCL = 2;
EP0CS |= bmHSNAK;
} else
{
operationMode=SETUPDAT[2];
if (operationMode==0)
{
TIMESTAMP_MODE = 0;
CFG_TIMESTAMP_COUNTER = 0;
}else if (operationMode==1)
{
CFG_TIMESTAMP_COUNTER = 1;
TIMESTAMP_MODE = 0;
}else if (operationMode==2)
{
CFG_TIMESTAMP_COUNTER = 0;
TIMESTAMP_MODE = 1;
}else if (operationMode==3)
{
CFG_TIMESTAMP_COUNTER = 1;
TIMESTAMP_MODE = 1;
}
*EP0BUF = SETUPDAT[1];
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
}
return(FALSE);
}*/
case VR_IS_TS_MASTER:
{
EP0BUF[0] = SETUPDAT[1];
EP0BUF[1]= TIMESTAMP_MASTER;
EP0BCH = 0;
EP0BCL = 2;
EP0CS |= bmHSNAK;
return(FALSE);
}
/* case VR_MISSED_EVENTS:
{
EX1=0;
EP0BUF[0] = SETUPDAT[1];
EP0BUF[4]= (missedEvents & 0xFF000000) >> 24;
EP0BUF[3]= (missedEvents & 0x00FF0000) >> 16;
EP0BUF[2]= (missedEvents & 0x0000FF00) >> 8;
EP0BUF[1]= missedEvents & 0x000000FF;
EP0BCH = 0;
EP0BCL = 5;
EP0CS |= bmHSNAK;
missedEvents=0;
EX1=1;
return(FALSE);
}*/
case VR_RAM:
case VR_EEPROM:
{
value = SETUPDAT[2]; // Get address and length
value |= SETUPDAT[3] << 8;
len = SETUPDAT[6];
len |= SETUPDAT[7] << 8;
// Is this an upload command ?
if(SETUPDAT[0] == VR_UPLOAD) // this is automatically defined on host from direction of vendor request
{
while(len) // Move requested data through EP0IN
{ // one packet at a time.
while(EP0CS & bmEPBUSY);
if(len < EP0BUFF_SIZE)
bc = len;
else
bc = EP0BUFF_SIZE;
// Is this a RAM upload ?
if(SETUPDAT[1] == VR_RAM)
{
for(i=0; i<bc; i++)
*(EP0BUF+i) = *((BYTE xdata *)value+i);
}
else
{
for(i=0; i<bc; i++)
*(EP0BUF+i) = 0xcd;
EEPROMRead(value,(WORD)bc,(WORD)EP0BUF);
}
EP0BCH = 0;
EP0BCL = (BYTE)bc; // Arm endpoint with # bytes to transfer
value += bc;
len -= bc;
}
}
// Is this a download command ?
else if(SETUPDAT[0] == VR_DOWNLOAD) // this is automatically defined on host from direction of vendor request
{
while(len) // Move new data through EP0OUT
{ // one packet at a time.
// Arm endpoint - do it here to clear (after sud avail)
EP0BCH = 0;
EP0BCL = 0; // Clear bytecount to allow new data in; also stops NAKing
while(EP0CS & bmEPBUSY);
bc = EP0BCL; // Get the new bytecount
// Is this a RAM download ?
if(SETUPDAT[1] == VR_RAM)
{
for(i=0; i<bc; i++)
*((BYTE xdata *)value+i) = *(EP0BUF+i);
}
else
EEPROMWrite(value,bc,(WORD)EP0BUF);
value += bc;
len -= bc;
}
}
return(FALSE);
}
default:
{ // we received an invalid command
return(TRUE);
}
}
*EP0BUF = SETUPDAT[1];
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
return(FALSE);
}
void Delay5us()
{
_nop_();
_nop_();
}
