static void gpio_unmask_irq(struct irq_data *d)
{
unsigned int gpio = irq_to_gpio(d->irq);
void __iomem *base = GPIO_BASE(gpio / 32);
_set_gpio_irqenable(base, gpio % 32, 1);
}
static void gpio_mask_irq(struct irq_data *d)
{
unsigned int gpio = irq_to_gpio(d->irq);
unsigned int base = GPIO_BASE(gpio / 32);
_set_gpio_irqenable(base, gpio % 32, 0);
}
static void gpio_unmask_irq(unsigned int irq)
{
unsigned int gpio = irq_to_gpio(irq);
unsigned int base = GPIO_BASE(gpio / 32);
_set_gpio_irqenable(base, gpio % 32, 1);
}
/*
* Enable a gpio pin's interrupt by clearing the bit in the imr.
* @param irq a gpio virtual irq number
*/
static void gpio_unmask_irq(u32 irq)
{
u32 gpio = MXC_IRQ_TO_GPIO(irq);
struct gpio_port *port = get_gpio_port(gpio);
_set_gpio_irqenable(port, GPIO_TO_INDEX(gpio), 1);
}
/*!
* Release ownership for a GPIO pin
* @param pin a name defined by \b iomux_pin_name_t
*/
void mxc_free_gpio(iomux_pin_name_t pin)
{
struct gpio_port *port;
u32 index, gpio = IOMUX_TO_GPIO(pin);
if (check_gpio(gpio) < 0)
return;
port = get_gpio_port(gpio);
index = GPIO_TO_INDEX(gpio);
spin_lock(&port->lock);
if ((!(port->reserved_map & (1 << index)))) {
printk(KERN_ERR "GPIO port %d, pin %d wasn't reserved!\n",
port->num, index);
dump_stack();
spin_unlock(&port->lock);
return;
}
port->reserved_map &= ~(1 << index);
port->irq_is_level_map &= ~(1 << index);
_set_gpio_direction(port, index, 1);
_set_gpio_irqenable(port, index, 0);
_clear_gpio_irqstatus(port, index);
spin_unlock(&port->lock);
}
static void cs75xx_gpio_mask_irq(struct irq_data *irqd)
{
unsigned irq = irqd->irq;
unsigned int gpio = irq_to_gpio(irq);
void __iomem *base = cs75xx_gpio_base[gpio / GPIO_BANK_SIZE];
_set_gpio_irqenable(base, gpio % GPIO_BANK_SIZE, 0);
}
static int cs75xx_gpio_set_irq_wake(struct irq_data *irqd, unsigned int on)
{
unsigned irq = irqd->irq;
unsigned int gpio = irq_to_gpio(irq);
void __iomem *base;
if (gpio >= (GPIO_BANK_NUM * GPIO_BANK_SIZE))
return -EINVAL;
base = cs75xx_gpio_base[gpio / GPIO_BANK_SIZE];
if (on) /* enter PM, GPIO irq will be disabled */
_set_gpio_irqenable(base, gpio % GPIO_BANK_SIZE, 1);
return 0;
}
static void gpio_unmask_irq(u32 irq)
{
u32 gpio = irq_to_gpio(irq);
_set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
}