void set_dvfs(unsigned int domain, unsigned int index)
{
int cur, to;
static int init_flag = 0;
if (!init_flag) {
pwm_init(pwm_f);
pwm_init(pwm_ao_a);
init_flag = 1;
}
cur = dvfs_get_voltage(domain);
for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
if (domain == 0) {
if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
break;
}
}
if (domain == 1) {
if (pwm_voltage_table[to][1] >= vlittle_dvfs_tbl[index].volt_mv) {
break;
}
}
}
if (to >= ARRAY_SIZE(pwm_voltage_table)) {
to = ARRAY_SIZE(pwm_voltage_table) - 1;
}
if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
if (domain == 0)
P_AO_PWM_PWM_A = pwm_voltage_table[to][0];
if (domain == 1)
P_PWM_PWM_F = pwm_voltage_table[to][0];
_udelay(200);
return ;
}
while (cur != to) {
/*
* if target step is far away from current step, don't change
* voltage by one-step-done. You should change voltage step by
* step to make sure voltage output is stable
*/
if (cur < to) {
if (cur < to - 3) {
cur += 3;
} else {
cur = to;
}
} else {
if (cur > to + 3) {
cur -= 3;
} else {
cur = to;
}
}
if (domain == 0)
P_AO_PWM_PWM_A = pwm_voltage_table[cur][0];
if (domain == 1)
P_PWM_PWM_F = pwm_voltage_table[to][0];
_udelay(100);
}
_udelay(200);
}
static void power_on_ee(void)
{
return;
aml_update_bits(AO_GPIO_O_EN_N, 1 << 8, 0);
aml_update_bits(AO_GPIO_O_EN_N, 1 << 24, 1 << 24);
_udelay(10000);
_udelay(10000);
}
static void power_off_at_32k(unsigned int suspend_from)
{
power_off_usb5v();
_udelay(5000);
power_off_3v3_5v();
_udelay(5000);
pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_SLEEP_VOLTAGE); /* reduce power */
if (suspend_from == SYS_POWEROFF) {
power_off_ee();
power_off_ddr();
}
}
void pwm_init(int id)
{
/*
* TODO: support more pwm controllers, right now only support PWM_B
*/
unsigned int reg;
reg = P_PWM_MISC_REG_AB;
reg &= ~(0x7f << 8);
reg |= ((1 << 15) | (1 << 0));
P_PWM_MISC_REG_AB = reg;
/*
* default set to max voltage
*/
P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
reg = P_PIN_MUX_REG3;
reg &= ~(1 << 21);
P_PIN_MUX_REG3 = reg;
reg = P_PIN_MUX_REG4;
reg &= ~(1 << 26); // clear PWM_VS
reg |= (1 << 17); // enable PWM_A
P_PIN_MUX_REG4 = reg;
_udelay(200);
}
void pwm_set_voltage(unsigned int id, unsigned int voltage)
{
int to;
uart_puts("set vddee to 0x");
uart_put_hex(voltage, 16);
uart_puts("mv\n");
for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
if (pwm_voltage_table[to][1] >= voltage) {
break;
}
}
if (to >= ARRAY_SIZE(pwm_voltage_table)) {
to = ARRAY_SIZE(pwm_voltage_table) - 1;
}
switch (id) {
case pwm_b:
P_PWM_PWM_B = pwm_voltage_table[to][0];
break;
case pwm_d:
P_PWM_PWM_D = pwm_voltage_table[to][0];
break;
default:
break;
}
_udelay(200);
}
static void power_on_at_32k(unsigned int suspend_from)
{
pwm_set_voltage(pwm_ao_b, CONFIG_VDDEE_INIT_VOLTAGE);
_udelay(10000);
power_on_3v3_5v();
_udelay(5000);
pwm_set_voltage(pwm_a, CONFIG_VCCK_INIT_VOLTAGE);
_udelay(10000);
_udelay(10000);
power_on_usb5v();
if (suspend_from == SYS_POWEROFF) {
power_on_ddr();
power_on_ee();
}
}
void board_init(void)
{
power_init(0);
//only run once before ddr inited.
if (!check_is_ddr_inited()) {
/* dram 1.5V reset */
serial_puts("DRAM reset...\n");
/* power off ddr */
writel((readl(P_AO_GPIO_O_EN_N) & (~((1 << 11) | (1 << 27)))),P_AO_GPIO_O_EN_N);
/* need delay, check hw design */
_udelay(400000);
/* power on ddr */
writel((readl(P_AO_GPIO_O_EN_N) | (1 << 27)),P_AO_GPIO_O_EN_N);
/* dram RC charge time, check hw design */
_udelay(10000);
}
panel_power_init();
}
static void power_switch_to_ee(unsigned int pwr_ctrl)
{
if (pwr_ctrl == ON) {
writel(readl(AO_RTI_PWR_CNTL_REG0) | (0x1 << 9), AO_RTI_PWR_CNTL_REG0);
_udelay(1000);
writel(readl(AO_RTI_PWR_CNTL_REG0)
& (~((0x3 << 3) | (0x1 << 1))), AO_RTI_PWR_CNTL_REG0);
} else {
writel(readl(AO_RTI_PWR_CNTL_REG0)
| ((0x3 << 3) | (0x1 << 1)), AO_RTI_PWR_CNTL_REG0);
writel(readl(AO_RTI_PWR_CNTL_REG0) & (~(0x1 << 9)),
AO_RTI_PWR_CNTL_REG0);
}
}
void pwm_set_voltage(unsigned int id, unsigned int voltage)
{
int to;
for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
if (pwm_voltage_table[to][1] >= voltage) {
break;
}
}
if (to >= ARRAY_SIZE(pwm_voltage_table)) {
to = ARRAY_SIZE(pwm_voltage_table) - 1;
}
//serial_put_dec( pwm_voltage_table[to][1]);
//serial_puts(" mv\n");
//serial_put_dec( pwm_voltage_table[to][0]);
//serial_puts(" mv\n");
switch (id) {
case pwm_a:
P_PWM_PWM_A = pwm_voltage_table[to][0];
break;
case pwm_ao_b:
P_AO_PWM_PWM_B = pwm_voltage_table[to][0];
break;
case pwm_f:
P_PWM_PWM_F = pwm_voltage_table[to][0];
break;
default:
break;
}
_udelay(200);
}
void udelay(unsigned long usecs)
{
_udelay(usecs);
}
void pwm_init(int id)
{
unsigned int reg;
/*
* TODO: support more pwm controllers, right now only support
* PWM_A, PWM_AO_B,PWM_F
*/
switch (id) {
case pwm_a:
reg = P_PWM_MISC_REG_AB;
reg &= ~(0x7f << 8);
reg |= ((1 << 15) | (1 << 0));
P_PWM_MISC_REG_AB = reg;
/*
* default set to max voltage
*/
P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
reg = P_PIN_MUX_REG10;
reg &= ~((1 << 12)|(1<<14)|(1<<22));
P_PIN_MUX_REG10 = reg;
reg = P_PIN_MUX_REG10;
reg |= (1 << 21); // enable PWM_A
P_PIN_MUX_REG10 = reg;
break;
case pwm_ao_b:
reg = P_AO_PWM_MISC_REG_AB;
reg &= ~(0x7f << 16);
reg |= ((1 << 23) | (1 << 1)|(1<<0));
P_AO_PWM_MISC_REG_AB = reg;
/*
* default set to max voltage
*/
P_AO_PWM_PWM_B = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
reg = P_PIN_MUX_AO;
reg &= ~(1 << 22);
P_PIN_MUX_AO = reg;
reg = P_PIN_MUX_AO;
reg |= (1 << 21); // enable PWM_AO_B
P_PIN_MUX_AO = reg;
break;
case pwm_f:
reg = P_PWM_MISC_REG_EF;
reg &= ~(0x7f << 16);
reg |= ((1 << 23) | (1 << 1) |(1 << 0));
P_PWM_MISC_REG_EF = reg;
/*
* default set to max voltage
*/
P_PWM_PWM_F = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
reg = P_PIN_MUX_AO;
reg &= ~(1 << 21);
P_PIN_MUX_AO = reg;
reg = P_PIN_MUX_AO;
reg |= (1 << 22); // enable PWM_f
P_PIN_MUX_AO = reg;
break;
default:
break;
}
_udelay(200);
}
static void power_on_ddr(void)
{
aml_update_bits(AO_GPIO_O_EN_N, 1 << 11, 0);
aml_update_bits(AO_GPIO_O_EN_N, 1 << 27, 1 << 27);
_udelay(10000);
}
