/* Let the GMU know that we are about to go into slumber */ static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) { int ret; /* Disable the power counter so the GMU isn't busy */ gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); /* Disable SPTP_PC if the CPU is responsible for it */ if (gmu->idle_level < GMU_IDLE_STATE_SPTP) a6xx_sptprac_disable(gmu); /* Tell the GMU to get ready to slumber */ gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); if (!ret) { /* Check to see if the GMU really did slumber */ if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) != 0x0f) { DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n"); ret = -ETIMEDOUT; } } /* Put fence into allow mode */ gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); return ret; }
static void __a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) { struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; struct msm_gpu *gpu = &adreno_gpu->base; int ret; gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, ((3 & 0xf) << 28) | index); /* * Send an invalid index as a vote for the bus bandwidth and let the * firmware decide on the right vote */ gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); /* Set and clear the OOB for DCVS to trigger the GMU */ a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); if (ret) dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret); gmu->freq = gmu->gpu_freqs[index]; /* * Eventually we will want to scale the path vote with the frequency but * for now leave it at max so that the performance is nominal. */ icc_set_bw(gpu->icc_path, 0, MBps_to_icc(7216)); }
/* Let the GMU know we are starting a boot sequence */ static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) { u32 vote; /* Let the GMU know we are getting ready for boot */ gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); /* Choose the "default" power level as the highest available */ vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); /* Let the GMU know the boot sequence has started */ return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); }
static int a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) { gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, ((index << 24) & 0xff) | (3 & 0xf)); /* * Send an invalid index as a vote for the bus bandwidth and let the * firmware decide on the right vote */ gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); /* Set and clear the OOB for DCVS to trigger the GMU */ a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); return gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); }