int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu) { struct a6xx_gmu *gmu = &a6xx_gpu->gmu; int ret; u32 val; /* Flush all the queues */ a6xx_hfi_stop(gmu); /* Stop the interrupts */ a6xx_gmu_irq_disable(gmu); /* Force off SPTP in case the GMU is managing it */ a6xx_sptprac_disable(gmu); /* Make sure there are no outstanding RPMh votes */ gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, (val & 1), 100, 10000); gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, (val & 1), 100, 10000); gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, (val & 1), 100, 10000); gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, (val & 1), 100, 1000); /* Force off the GX GSDC */ regulator_force_disable(gmu->gx); /* Disable the resources */ clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); pm_runtime_put_sync(gmu->dev); /* Re-enable the resources */ pm_runtime_get_sync(gmu->dev); /* Use a known rate to bring up the GMU */ clk_set_rate(gmu->core_clk, 200000000); ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); if (ret) goto out; a6xx_gmu_irq_enable(gmu); ret = a6xx_gmu_fw_start(gmu, GMU_RESET); if (!ret) ret = a6xx_hfi_start(gmu, GMU_COLD_BOOT); /* Set the GPU back to the highest power frequency */ a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1); out: if (ret) a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); return ret; }
int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { struct a6xx_gmu *gmu = &a6xx_gpu->gmu; int status, ret; if (WARN(!gmu->mmio, "The GMU is not set up yet\n")) return 0; /* Turn on the resources */ pm_runtime_get_sync(gmu->dev); /* Use a known rate to bring up the GMU */ clk_set_rate(gmu->core_clk, 200000000); ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); if (ret) goto out; a6xx_gmu_irq_enable(gmu); /* Check to see if we are doing a cold or warm boot */ status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? GMU_WARM_BOOT : GMU_COLD_BOOT; ret = a6xx_gmu_fw_start(gmu, status); if (ret) goto out; ret = a6xx_hfi_start(gmu, status); /* Set the GPU to the highest power frequency */ a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1); out: /* Make sure to turn off the boot OOB request on error */ if (ret) a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); return ret; }
int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; struct msm_gpu *gpu = &adreno_gpu->base; struct a6xx_gmu *gmu = &a6xx_gpu->gmu; int status, ret; if (WARN(!gmu->initialized, "The GMU is not set up yet\n")) return 0; gmu->hung = false; /* Turn on the resources */ pm_runtime_get_sync(gmu->dev); /* Use a known rate to bring up the GMU */ clk_set_rate(gmu->core_clk, 200000000); ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); if (ret) { pm_runtime_put(gmu->dev); return ret; } /* Set the bus quota to a reasonable value for boot */ icc_set_bw(gpu->icc_path, 0, MBps_to_icc(3072)); /* Enable the GMU interrupt */ gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK); enable_irq(gmu->gmu_irq); /* Check to see if we are doing a cold or warm boot */ status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? GMU_WARM_BOOT : GMU_COLD_BOOT; ret = a6xx_gmu_fw_start(gmu, status); if (ret) goto out; ret = a6xx_hfi_start(gmu, status); if (ret) goto out; /* * Turn on the GMU firmware fault interrupt after we know the boot * sequence is successful */ gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK); enable_irq(gmu->hfi_irq); /* Set the GPU to the highest power frequency */ __a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1); /* * "enable" the GX power domain which won't actually do anything but it * will make sure that the refcounting is correct in case we need to * bring down the GX after a GMU failure */ if (!IS_ERR_OR_NULL(gmu->gxpd)) pm_runtime_get(gmu->gxpd); out: /* On failure, shut down the GMU to leave it in a good state */ if (ret) { disable_irq(gmu->gmu_irq); a6xx_rpmh_stop(gmu); pm_runtime_put(gmu->dev); } return ret; }