void activecpu_eat_cycles(int cycles)
{
int cyclesleft = activecpu_get_icount();
if (cycles > cyclesleft)
cycles = cyclesleft;
activecpu_adjust_icount(-cycles);
}
void activecpu_abort_timeslice(void)
{
int current_icount;
VERIFY_EXECUTINGCPU_VOID(activecpu_abort_timeslice);
LOG(("activecpu_abort_timeslice (CPU=%d, cycles_left=%d)\n", cpu_getexecutingcpu(), activecpu_get_icount() + 1));
/* swallow the remaining cycles */
current_icount = activecpu_get_icount() + 1;
cycles_stolen += current_icount;
cycles_running -= current_icount;
activecpu_adjust_icount(-current_icount);
}
/*
TMS5200 speech chip write
*/
static WRITE8_HANDLER ( geneve_speech_w )
{
activecpu_adjust_icount(-32*4); /* this is just an approx. minimum, it can be much more */
#if 1
/* the stupid design of the tms5220 core means that ready is cleared when
there are 15 bytes in FIFO. It should be 16. Of course, if it were the
case, we would need to store the value on the bus, which would be more
complex. */
if (! tms5220_ready_r())
{
double time_to_ready = tms5220_time_to_ready();
int cycles_to_ready = ceil(TIME_TO_CYCLES(0, time_to_ready));
logerror("time to ready: %f -> %d\n", time_to_ready, (int) cycles_to_ready);
activecpu_adjust_icount(-cycles_to_ready);
timer_set(TIME_NOW, 0, /*speech_kludge_callback*/NULL);
}
#endif
tms5220_data_w(offset, data);
}
static UINT32 ide_controller_read(struct ide_state *ide, offs_t offset, int size)
{
UINT32 result = 0;
/* logit */
if (offset != IDE_ADDR_DATA && offset != IDE_ADDR_STATUS_COMMAND && offset != IDE_ADDR_STATUS_CONTROL)
LOG(("%08X:IDE read at %03X, size=%d\n", activecpu_get_previouspc(), offset, size));
switch (offset)
{
/* unknown config register */
case IDE_ADDR_CONFIG_UNK:
return ide->config_unknown;
/* active config register */
case IDE_ADDR_CONFIG_REGISTER:
return ide->config_register_num;
/* data from active config register */
case IDE_ADDR_CONFIG_DATA:
if (ide->config_register_num < IDE_CONFIG_REGISTERS)
return ide->config_register[ide->config_register_num];
return 0;
/* read data if there's data to be read */
case IDE_ADDR_DATA:
if (ide->status & IDE_STATUS_BUFFER_READY)
{
/* fetch the correct amount of data */
result = ide->buffer[ide->buffer_offset++];
if (size > 1)
result |= ide->buffer[ide->buffer_offset++] << 8;
if (size > 2)
{
result |= ide->buffer[ide->buffer_offset++] << 16;
result |= ide->buffer[ide->buffer_offset++] << 24;
}
/* if we're at the end of the buffer, handle it */
if (ide->buffer_offset >= IDE_DISK_SECTOR_SIZE)
continue_read(ide);
}
break;
/* return the current error */
case IDE_ADDR_ERROR:
return ide->error;
/* return the current sector count */
case IDE_ADDR_SECTOR_COUNT:
return ide->sector_count;
/* return the current sector */
case IDE_ADDR_SECTOR_NUMBER:
return ide->cur_sector;
/* return the current cylinder LSB */
case IDE_ADDR_CYLINDER_LSB:
return ide->cur_cylinder & 0xff;
/* return the current cylinder MSB */
case IDE_ADDR_CYLINDER_MSB:
return ide->cur_cylinder >> 8;
/* return the current head */
case IDE_ADDR_HEAD_NUMBER:
return ide->cur_head_reg;
/* return the current status and clear any pending interrupts */
case IDE_ADDR_STATUS_COMMAND:
/* return the current status but don't clear interrupts */
case IDE_ADDR_STATUS_CONTROL:
result = ide->status;
if (timer_timeelapsed(ide->last_status_timer) > TIME_PER_ROTATION)
{
result |= IDE_STATUS_HIT_INDEX;
timer_adjust(ide->last_status_timer, TIME_NEVER, 0, 0);
}
/* clear interrutps only when reading the real status */
if (offset == IDE_ADDR_STATUS_COMMAND)
{
if (ide->interrupt_pending)
clear_interrupt(ide);
}
/* take a bit of time to speed up people who poll hard */
activecpu_adjust_icount(-100);
break;
/* log anything else */
default:
logerror("%08X:unknown IDE read at %03X, size=%d\n", activecpu_get_previouspc(), offset, size);
break;
}
/* return the result */
return result;
}
/*
TMS5200 speech chip read
*/
static READ8_HANDLER ( geneve_speech_r )
{
activecpu_adjust_icount(-8); /* this is just a minimum, it can be more */
return tms5220_status_r(offset);
}
