static READ8_HANDLER( dorachan_protection_r )
{
switch (activecpu_get_previouspc())
{
case 0x70ce : return 0xf2;
case 0x72a2 : return 0xd5;
case 0x72b5 : return 0xcb;
}
printf("unhandled $2400 read @ %x\n",activecpu_get_previouspc());
return 0xff;
}
static READ32_HANDLER( speedup_r )
{
int result = *speedup_data;
if ((activecpu_get_previouspc() & 0xfffff) == 0x006f0 && result == activecpu_get_reg(ASAP_R3))
cpu_spinuntil_int();
return result;
}
static READ16_HANDLER( bankrom_r )
{
/* this is the banked ROM read */
logerror("%06X: %04X\n", activecpu_get_previouspc(), offset);
/* if the values are $3e000 or $3e002 are being read by code just below the
ROM bank area, we need to return the correct value to give the proper checksum */
if ((offset == 0x3000 || offset == 0x3001) && activecpu_get_previouspc() > 0x37000)
{
unsigned int checksum = (program_read_word(0x3fd210)<<16)|program_read_word(0x3fd212);
unsigned int us = 0xaaaa5555 - checksum;
if (offset == 0x3001)
return us & 0xffff;
else
return us >> 16;
}
static WRITE_HANDLER(by8035_ram_w) {
UINT8 *ram = memory_region(REGION_CPU1) + 0x5000 + 0x100 * locals.ramBank;
ram[offset] = data;
if (locals.ramBank == 0x0b) locals.segments[offset].w = (~data & 0x7f) | ((~data & 0x80) << 1) | ((~data & 0x80) << 2);
if (locals.ramBank > 7) logerror("%04x: ram %03x write: %02x\n", activecpu_get_previouspc(), 0x100 * locals.ramBank + offset, data);
// if (locals.ramBank == 0x0a) ppi8255_0_w(offset & 3, data);
}
static READ_HANDLER(by8035_ram_r) {
UINT8 *ram = memory_region(REGION_CPU1) + 0x5000 + 0x100 * locals.ramBank;
if (locals.ramBank > 7) logerror("%04x: ram %03x read\n", activecpu_get_previouspc(), 0x100 * locals.ramBank + offset);
if (offset == 2) return 0x55;
// if (ram_bank == 0x0a) return ppi8255_0_r(offset & 3);
return ram[offset];
}
static WRITE8_HANDLER(audio_w)
{
if(activecpu_get_previouspc()==0x2fd)
{
nAyCtrl=offset;
nAyData=data;
}
}
static WRITE_HANDLER(by8035_port_w) {
if (offset == 2)
{
cpu_setbank(1, memory_region(REGION_CPU1) + 0x1000 + 0x100 * (data & 0x30));
locals.ramBank = data & 0x0f;
}
logerror("%04x: 8035 port %d write = %02x\n", activecpu_get_previouspc(), offset, data);
}
static WRITE8_HANDLER(ay1_sel)
{
if(activecpu_get_previouspc()==0x309)
{
AY8910_control_port_0_w(0,nAyCtrl);
AY8910_write_port_0_w(0,nAyData);
}
}
/*
static READ8_HANDLER( rom_bank_select_r )
{
return suprgolf_rom_bank;
}
*/
static WRITE8_HANDLER( rom_bank_select_w )
{
UINT8 *region_base = memory_region(REGION_USER1);
suprgolf_rom_bank = data;
printf("ROM_BANK 0x8000 - %X @%X\n",data,activecpu_get_previouspc());
memory_set_bankptr(2, region_base + (data&0x3f ) * 0x4000);
}
static READ16_HANDLER( backup_ram_dx_r )
{
/*TODO: understand the format & cmds of the backup-ram,maybe it's an
unemulated tmp68301 feature?*/
if(activecpu_get_previouspc() == 0x02f046)
return 0xffff;
else
return backup_ram[offset];
}
static READ16_HANDLER( bmc_protection_r )
{
switch(activecpu_get_previouspc())
{
case 0xca68:
switch(activecpu_get_reg(M68K_D2))
{
case 0:
return 0x37<<8;
case 0x1013:
return 0;
default:
return 0x46<<8;
}
break;
}
logerror("Protection read @ %X\n",activecpu_get_previouspc());
return mame_rand(Machine);
}
// ok
static READ_HANDLER(snd300_r) {
logerror("%04x: snd300_r adress A%c data latch %02x give %02x \n", activecpu_get_previouspc(), debugms[offset],snddatst300.ax[offset],snddatst300.axb[offset]);
snddatst300.axb[2] = snddatst300.timer1 / 256;
snddatst300.axb[3] = snddatst300.timer1 - (snddatst300.axb[2] * 256);
snddatst300.axb[4] = snddatst300.timer2 / 256;
snddatst300.axb[5] = snddatst300.timer2 - (snddatst300.axb[4] * 256);
snddatst300.axb[6] = snddatst300.timer3 / 256;
snddatst300.axb[7] = snddatst300.timer3 - (snddatst300.axb[6] * 256);
return snddatst300.axb[offset];
}
static READ32_HANDLER( movie_speedup_r )
{
int result = *movie_speedup_data;
if ((activecpu_get_previouspc() & 0xfffff) == 0x00a88 && (activecpu_get_reg(ASAP_R28) & 0xfffff) == 0x397c0 &&
movie_speedup_data[4] == activecpu_get_reg(ASAP_R1))
{
UINT32 temp = (INT16)result + movie_speedup_data[4] * 262;
if (temp - (UINT32)activecpu_get_reg(ASAP_R15) < (UINT32)activecpu_get_reg(ASAP_R23))
cpu_spinuntil_int();
}
return result;
}
/*
Write transmit register
*/
void acia6850_data_w(int which, UINT8 data)
{
if (!acia[which].reset)
{
acia[which].tdr = data;
timer_set(TIME_NOW, which, tdr_to_shift);
//printf("ACIA %d Transmit: %x (%c)\n", which, data, data);
}
else
{
logerror("ACIA %d: Data write while in reset! (%x)\n", which, activecpu_get_previouspc());
}
}
/* Above prom also at 16s and 17s */
ROM_END
/**********************************************************************************/
static READ16_HANDLER( dassault_main_skip )
{
int ret=dassault_ram[0];
if (activecpu_get_previouspc()==0x1170 && ret&0x8000)
cpu_spinuntil_int();
return ret;
}
static READ_HANDLER(port_r) {
UINT8 *ram = memory_region(REGION_CPU1) + 0x1000;
UINT8 retVal = ram[offset];
logerror("%03x: R%x %02x - %02x\n", activecpu_get_previouspc(), locals.p2 >> 4, offset, locals.p1);
switch (locals.p2 >> 4) {
case 0: retVal = ~core_revbyte(coreGlobals.swMatrix[1 + core_BitColToNum(0xff ^ locals.p1)]); break;
// case 1: unused by code, possible expansion (J4-7)
case 4: retVal = core_getDip(0); break;
case 5: retVal = core_getDip(1); break;
case 6: retVal = core_getDip(3); printf("DIP3 used!!!"); break; // unused, so place it at the end and don't map it
case 7: retVal = core_getDip(2); break;
}
return retVal;
}
AM_RANGE(0xfd00, 0xffff) AM_RAM
ADDRESS_MAP_END
static WRITE8_HANDLER(ppmast_sound_w)
{
switch(offset&0xff)
{
case 0: YM2413_register_port_0_w(0,data); break;
case 1: YM2413_data_port_0_w(0,data); break;
case 2: DAC_0_data_w(0,data);break;
default: logerror("%x %x - %x\n",offset,data,activecpu_get_previouspc());
}
}
INPUT_PORTS_END
static READ8_HANDLER(dips1_r)
{
switch(bmc_input)
{
case 0x00:
return input_port_1_r(0);
case 0x40:
return input_port_2_r(0);
}
logerror("unknown input - %X (PC=%X)\n",bmc_input,activecpu_get_previouspc());
return 0xff;
}
/*
Write transmit register
*/
static void acia6850_data_w(int which, UINT8 data)
{
acia_6850 *acia_p = &acia[which];
if (!acia_p->reset)
{
acia_p->tdr = data;
acia_p->status &= ~ACIA6850_STATUS_TDRE;
acia6850_check_interrupts(which);
}
else
{
logerror("ACIA %d: Data write while in reset! (%x)\n", which, activecpu_get_previouspc());
}
}
static WRITE8_HANDLER( trvmadns_tileram_w )
{
if(offset==0)
{
if(activecpu_get_previouspc()==0x29e9)// || activecpu_get_previouspc()==0x1b3f) //29f5
{
cpunum_set_input_line(machine, 0, 0, HOLD_LINE);
}
// else
// printf("%x \n", activecpu_get_previouspc());
}
trvmadns_tileram[offset] = data;
tilemap_mark_tile_dirty(bg_tilemap,offset >> 1);
}
static READ8_HANDLER(data_408_r)
{
/*
Hot Smash
select_408=1 && bit 7==1 -> protection related ?
Setting this bit to high cause win/lose/game over etc
(see below)
*/
switch(select_408)
{
case 0: return 0; //pb?
case 1: return is_pbillian?input_port_3_r(0):((spriteram[0x20]&1)?0x8c:input_port_3_r(0));
/*
written by mcu ? (bit 7=1) (should be sequence of writes , 0x88+0x8c for example)
0x82 = no ball
0x83 = time over
0x84 = P1 score++
0x86 = 0-1
0x87 = 1-0
0x88 = P1 WIN
0x89 = Game Over
0x8a = restart P1 side
0x8b = restart P2 side
0x8c = next level + restart
*/
case 2: return input_port_4_r(0);
case 4: return input_port_0_r(0);
case 8: return input_port_1_r(0);
case 0x20: return 0; //pb ?
case 0x80: return 0; //pb?
case 0xf0: return 0; //hs?
}
logerror("408[%x] r at %x\n",select_408,activecpu_get_previouspc());
return 0;
}
static WRITE32_HANDLER( control_w )
{
// bit $80000000 = BSMT access/ROM read
// bit $20000000 = toggled every 64 IRQ4's
// bit $10000000 = ????
// bit $00800000 = EEPROM data
// bit $00400000 = EEPROM clock
// bit $00200000 = EEPROM enable (on 1)
COMBINE_DATA(&control_data);
/* handle EEPROM I/O */
if (!(mem_mask & 0x00ff0000))
{
EEPROM_write_bit(data & 0x00800000);
EEPROM_set_cs_line((data & 0x00200000) ? CLEAR_LINE : ASSERT_LINE);
EEPROM_set_clock_line((data & 0x00400000) ? ASSERT_LINE : CLEAR_LINE);
}
/* log any unknown bits */
if (data & 0x4f1fffff)
logerror("%08X: control_w = %08X & %08X\n", activecpu_get_previouspc(), data, ~mem_mask);
}
static WRITE32_HANDLER( speedup_w )
{
COMBINE_DATA(speedup_data);
/* see if the PC matches */
if ((activecpu_get_previouspc() & 0x1fffffff) == speedup_pc)
{
UINT32 curr_cycles = activecpu_gettotalcycles();
/* if less than 50 cycles from the last time, count it */
if (curr_cycles - last_cycles < 50)
{
loop_count++;
/* more than 2 in a row and we spin */
if (loop_count > 2)
cpu_spinuntil_int();
}
else
loop_count = 0;
last_cycles = curr_cycles;
}
}
static void delayed_command_w(int data)
{
pia_0_porta_w(0, data);
pia_0_ca1_w(0, 0);
if (LOG_SOUND) logerror("%04X:!!!! Sound command = %02X\n", activecpu_get_previouspc(), data);
}
static READ8_HANDLER( sound_status_r )
{
if (LOG_SOUND) logerror("%04X:!!!! Sound status read = %02X\n", activecpu_get_previouspc(), (pia_0_ca1_r(0) << 7) | (pia_0_cb1_r(0) << 6));
return (pia_0_ca1_r(0) << 7) | (pia_0_cb1_r(0) << 6);
}
static READ8_HANDLER( sound_response_r )
{
if (LOG_SOUND) logerror("%04X:!!!! Sound response read = %02X\n", activecpu_get_previouspc(), sound_response);
pia_0_cb1_w(0, 0);
return sound_response;
}
static WRITE_HANDLER(data_port_w)
{
logerror("%04x: Data Port Write=%02x\n",activecpu_get_previouspc(),data);
}
static READ_HANDLER(sense_port_r)
{
logerror("%04x: Sense Port Read\n",activecpu_get_previouspc());
return 0;
}
static READ_HANDLER(data_port_r)
{
logerror("%04x: Data Port Read\n",activecpu_get_previouspc());
return 0;
}
static READ_HANDLER(ctrl_port_r)
{
logerror("%04x: Ctrl Port Read\n",activecpu_get_previouspc());
return 0;
}