/***************************************************************************//**
* @brief Writes parameters to the AD9122.
*
* @return Returns negative error code or 0 in case of success.
*******************************************************************************/
int32_t ad9122_write_raw(uint32_t channel,
int32_t val,
int32_t val2,
int32_t mask)
{
struct cf_axi_converter *conv = &dds_conv;
uint32_t rate;
int32_t ret;
uint32_t ctrl_reg_1;
uint32_t ctrl_reg_2;
DAC_Core_Read(ADI_REG_CNTRL_1, &ctrl_reg_1);
DAC_Core_Read(ADI_REG_CNTRL_2, &ctrl_reg_2);
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
rate = ad9122_get_data_clk(conv);
ret = ad9122_set_data_clk(conv, val);
if (ret < 0) {
return ret;
}
if (val != rate) {
ret = ad9122_tune_dci(conv);
}
break;
default:
return -1;
}
DAC_Core_Write(ADI_REG_CNTRL_1, ctrl_reg_1);
DAC_Core_Write(ADI_REG_CNTRL_2, ctrl_reg_2);
return ret;
}
/***************************************************************************//**
* @brief Writes parameters to the AD9122.
*
* @return Returns negative error code or 0 in case of success.
*******************************************************************************/
int32_t ad9122_write_raw(uint32_t channel,
int32_t val,
int32_t val2,
int32_t mask)
{
struct cf_axi_converter *conv = &dds_conv;
uint32_t rate;
int32_t ret;
switch (mask) {
case IIO_CHAN_INFO_SAMP_FREQ:
rate = ad9122_get_data_clk(conv);
ret = ad9122_set_data_clk(conv, val);
if (ret < 0) {
return ret;
}
if (val != rate) {
ad9122_tune_dci(conv);
}
break;
default:
return -1;
}
return 0;
}
/***************************************************************************//**
* @brief Sets the interpolation factor and the center shift frequency.
*
* @param conv - Pointer to a cf_axi_converter struct.
* @param interp - Interpolation factor
* @param fcent_shift - Center frequency shift as a multiplier of fData / 2.
* The shift values should be in the range [0, 15]
* @param data_rate - Data rate in Hz
*
* @return Returns negative error code or 0 in case of success.
*******************************************************************************/
static int32_t ad9122_set_interpol(struct cf_axi_converter *conv,
uint32_t interp,
uint32_t fcent_shift,
uint32_t data_rate)
{
uint32_t hb1, hb2, hb3, tmp;
int32_t ret, cached;
hb1 = AD9122_HB1_CTRL_BYPASS_HB1;
hb2 = AD9122_HB2_CTRL_BYPASS_HB2;
hb3 = AD9122_HB3_CTRL_BYPASS_HB3;
switch (interp) {
case 1:
break;
case 2:
if (fcent_shift > 3)
return -1;
hb1 = AD9122_HB1_INTERP(fcent_shift);
break;
case 4:
if (fcent_shift > 7)
return -1;
hb1 = AD9122_HB1_INTERP(fcent_shift % 4);
hb2 = AD9122_HB23_INTERP(fcent_shift);
break;
case 8:
if (fcent_shift > 15)
return -1;
hb1 = AD9122_HB1_INTERP(fcent_shift % 4);
hb2 = AD9122_HB23_INTERP(fcent_shift % 8);
hb3 = AD9122_HB23_INTERP(fcent_shift / 2);
break;
default:
return -1;
}
cached = conv->interp_factor;
conv->interp_factor = interp;
ret = ad9122_set_data_clk(conv, data_rate ?
data_rate : ad9122_get_data_clk(conv));
if (ret < 0) {
conv->interp_factor = cached;
return ret;
}
tmp = ad9122_read(AD9122_REG_DATAPATH_CTRL);
switch (hb1) {
case AD9122_HB1_INTERP(1):
case AD9122_HB1_INTERP(3):
tmp &= ~AD9122_DATAPATH_CTRL_BYPASS_PREMOD;
break;
default:
tmp |= AD9122_DATAPATH_CTRL_BYPASS_PREMOD;
}
ad9122_write(AD9122_REG_DATAPATH_CTRL, tmp);
ad9122_write(AD9122_REG_HB1_CTRL, hb1);
ad9122_write(AD9122_REG_HB2_CTRL, hb2);
ad9122_write(AD9122_REG_HB3_CTRL, hb3);
conv->fcenter_shift = fcent_shift;
return 0;
}
