/* write a word to wishbone */
int dbg_wb_write32(unsigned long adr, unsigned long data) {
int err;
pthread_mutex_lock(&dbg_access_mutex);
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
{
if ((err = adbg_select_module(DC_WISHBONE)))
{
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
err = adbg_wb_burst_write((void *)&data, 4, 1, adr);
}
else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
{
data = ntohl(data);
if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_WISHBONE)))
if (APP_ERR_NONE == (err = legacy_dbg_command(0x2, adr, 4)))
err = legacy_dbg_go((unsigned char*)&data, 4, 0);
}
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
/* write multiple cpu registers to cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */
int dbg_cpu0_write_block(unsigned long adr, unsigned long *data, int count) {
int err;
pthread_mutex_lock(&dbg_access_mutex);
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
{
if ((err = adbg_select_module(DC_CPU0)))
{
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
err = adbg_wb_burst_write((void *)data, 4, count, adr);
}
else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
{
int i;
unsigned long writeaddr = adr;
err = APP_ERR_NONE;
for(i = 0; i < count; i++) {
err |= dbg_cpu0_write(writeaddr++, data[i]);
}
}
debug("cpu0_write_block, adr 0x%X, data[0] 0x%X, count %i, ret %i\n", adr, data[0], count, err);
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
// write a block to wishbone
// Never actually called from the GDB interface
int dbg_wb_write_block16(unsigned long adr, uint16_t *data, int len) {
int err;
pthread_mutex_lock(&dbg_access_mutex);
if(!len)
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
{
if ((err = adbg_select_module(DC_WISHBONE)))
{
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
err = adbg_wb_burst_write((void *)data, 2, len, adr); // 'len' is (half)words
}
else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
{
int i;
int bytelen = len<<1;
for (i = 0; i < len; i ++) data[i] = ntohs(data[i]);
if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_WISHBONE)))
if (APP_ERR_NONE == (err = legacy_dbg_command(0x1, adr, bytelen)))
err = legacy_dbg_go((unsigned char*)data, bytelen, 0); // 'len' is 16-bit halfwords, call wants bytes
}
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
// write a block to wishbone
int dbg_wb_write_block8(unsigned long adr, uint8_t *data, int len) {
int err;
pthread_mutex_lock(&dbg_access_mutex);
if(!len)
return APP_ERR_NONE; // GDB may issue a 0-length transaction to test if a feature is supported
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
{
if ((err = adbg_select_module(DC_WISHBONE)))
{
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
err = adbg_wb_burst_write((void *)data, 1, len, adr); // 'len' is in words...
}
else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
{
if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_WISHBONE)))
if (APP_ERR_NONE == (err = legacy_dbg_command(0x0, adr, len)))
err = legacy_dbg_go((unsigned char*)data, len, 0);
}
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
/* write a cpu register to cpu0. This is assumed to be an OR32 CPU, with 32-bit regs. */
int dbg_cpu0_write(uint32_t adr, uint32_t data) {
int err;
pthread_mutex_lock(&dbg_access_mutex);
if(DEBUG_HARDWARE == DBG_HW_ADVANCED)
{
if ((err = adbg_select_module(DC_CPU0)))
{
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
err = adbg_wb_burst_write((void *)&data, 4, 1, adr);
}
else if(DEBUG_HARDWARE == DBG_HW_LEGACY)
{
data = ntohl(data);
if (APP_ERR_NONE == (err = legacy_dbg_set_chain(DC_CPU0)))
if (APP_ERR_NONE == (err = legacy_dbg_command(0x2, adr, 4)))
err = legacy_dbg_go((unsigned char*)&data, 4, 0);
}
debug("cpu0_write, adr 0x%X, data 0x%X, ret %i\n", adr, data, err);
cable_flush();
pthread_mutex_unlock(&dbg_access_mutex);
return err;
}
