/**
* \brief Read multiple samples from ADC.
*
* Read \c samples samples from the ADC into the buffer \c buffer.
* If there is no hardware trigger defined (event action) the
* driver will retrigger the ADC conversion whenever a conversion
* is complete until \c samples samples has been acquired. To avoid
* jitter in the sampling frequency using an event trigger is advised.
*
* \param[in] module_inst Pointer to the ADC software instance struct
* \param[in] samples Number of samples to acquire
* \param[out] buffer Buffer to store the ADC samples
*
* \return Status of the job start.
* \retval STATUS_OK The conversion job was started successfully and is
* in progress
* \retval STATUS_BUSY The ADC is already busy with another job
*/
enum status_code adc_read_buffer_job(
struct adc_module *const module_inst,
uint16_t *buffer,
uint16_t samples)
{
Assert(module_inst);
Assert(samples);
Assert(buffer);
if(module_inst->remaining_conversions != 0 ||
module_inst->job_status == STATUS_BUSY) {
return STATUS_BUSY;
}
module_inst->job_status = STATUS_BUSY;
module_inst->remaining_conversions = samples;
module_inst->job_buffer = buffer;
adc_enable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY);
if(module_inst->software_trigger == true) {
adc_start_conversion(module_inst);
}
return STATUS_OK;
}
/**
* \brief Set callback for ADC
*
* \param dev_inst Device structure pointer.
* \param source interrupt source.
* \param callback callback function pointer.
* \param irq_line interrupt line.
* \param irq_level interrupt level.
*/
void adc_set_callback(struct adc_dev_inst *const dev_inst,
adc_interrupt_source_t source, adc_callback_t callback,
uint8_t irq_line, uint8_t irq_level)
{
adc_callback_pointer = callback;
irq_register_handler((IRQn_Type) irq_line, irq_level);
adc_enable_interrupt(dev_inst, source);
}
/* Initialize ADC */
static void adc_initialisation()
{
/* Enable a peripherals clock */
sysclk_enable_peripheral_clock(&ADC);
/* set prescaler and enable ADC */
adc_init(ADC_PRESCALER_DIV128);
/* set voltage reference, mux input and right adjustment */
adc_set_admux(ADC_VREF_AVCC | ADC_MUX_ADC0 | ADC_ADJUSTMENT_RIGHT);
adc_enable_interrupt();
}
/**
* \brief adc_temp_sensor Application entry point.
*
* Initialize adc to 12-bit, enable channel 15,turn on
* temp sensor, pdc channel interrupt for temp sensor
* and start conversion.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
/* Initialize the SAM system. */
sysclk_init();
board_init();
/* Disable watchdog. */
WDT->WDT_MR = WDT_MR_WDDIS;
configure_console();
/* Output example information. */
puts(STRING_HEADER);
/* 10 ms timer */
if (SysTick_Config(sysclk_get_cpu_hz() / 100)) {
puts("-F- Systick configuration error\r");
while (1) {
}
}
/* Enable peripheral clock. */
pmc_enable_periph_clk(ID_ADC);
/* Initialize ADC. */
/* startup = 8: 512 periods of ADCClock
* for prescale = 4
* prescale: ADCClock = MCK / ( (PRESCAL+1) * 2 ) => 64MHz / ((4+1)*2) = 6.4MHz
* ADC clock = 6.4 MHz
*/
adc_init(ADC, sysclk_get_cpu_hz(), 6400000, 8);
adc_configure_timing(ADC, 0, ADC_SETTLING_TIME_3, 1);
adc_configure_trigger(ADC, ADC_TRIG_SW, 0);
adc_check(ADC, sysclk_get_cpu_hz());
/* Enable channel for potentiometer. */
adc_enable_channel(ADC, ADC_TEMPERATURE_SENSOR);
/* Enable the temperature sensor. */
adc_enable_ts(ADC);
/* Enable ADC interrupt. */
NVIC_EnableIRQ(ADC_IRQn);
/* Start conversion. */
adc_start(ADC);
adc_read_buffer(ADC, gs_s_adc_values, BUFFER_SIZE);
/* Enable PDC channel interrupt. */
adc_enable_interrupt(ADC, ADC_ISR_RXBUFF);
while (1) {
}
}
/**
* \brief Set callback for ADC
*
* \param adc Base address of the ADC
* \param source Interrupt source
* \param callback Callback function pointer
* \param irq_level Interrupt level
*/
void adc_set_callback(Adc *const adc, enum adc_interrupt_source source,
adc_callback_t callback, uint8_t irq_level)
{
Assert(adc);
Assert(callback);
adc_callback_pointer[source] = callback;
irq_register_handler(ADC_IRQn, irq_level);
/* Enable the specified interrupt source */
adc_enable_interrupt(adc, source);
}
void configure_ADC(void){
/* Enable peripheral clock. */
pmc_enable_periph_clk(ID_ADC);
/* Initialize ADC. */
/*
* Formula: ADCClock = MCK / ( (PRESCAL+1) * 2 )
* For example, MCK = 64MHZ, PRESCAL = 4, then:
* ADCClock = 64 / ((4+1) * 2) = 6.4MHz;
*/
/* Formula:
* Startup Time = startup value / ADCClock
* Startup time = 64 / 6.4MHz = 10 us
*/
adc_init(ADC, sysclk_get_cpu_hz(), 6400000, STARTUP_TIME);
/* Formula:
* Transfer Time = (TRANSFER * 2 + 3) / ADCClock
* Tracking Time = (TRACKTIM + 1) / ADCClock
* Settling Time = settling value / ADCClock
*
* Transfer Time = (1 * 2 + 3) / 6.4MHz = 781 ns
* Tracking Time = (1 + 1) / 6.4MHz = 312 ns
* Settling Time = 3 / 6.4MHz = 469 ns
*/
adc_configure_timing(ADC, TRACKING_TIME , ADC_SETTLING_TIME_3, TRANSFER_PERIOD);
/*
* Configura trigger por software
*/
adc_configure_trigger(ADC, ADC_TRIG_SW, 0);
/*
* Checa se configuração
*/
//adc_check(ADC, sysclk_get_cpu_hz());
/* Enable channel for potentiometer. */
adc_enable_channel(ADC, ADC_POT_CHANNEL);
/* Enable ADC interrupt. */
NVIC_EnableIRQ(ADC_IRQn);
/* Start conversion. */
adc_start(ADC);
/* Enable PDC channel interrupt. */
adc_enable_interrupt(ADC, ADC_ISR_RXBUFF);
}
void configure_adc(void)
{
/* Enable peripheral clock. */
pmc_enable_periph_clk(ID_ADC);
adc_init(ADC, sysclk_get_cpu_hz(), 6400000, STARTUP_TIME);
adc_configure_timing(ADC, TRACKING_TIME , ADC_SETTLING_TIME_3, TRANSFER_PERIOD);
adc_configure_trigger(ADC, ADC_TRIG_SW, 0);
/* Enable chnnel for potentiometer. */
adc_enable_channel(ADC, ADC_POT_CHANNEL);
/* Enable ADC interrupt. */
NVIC_EnableIRQ(ADC_IRQn);
/* Start conversion. */
adc_start(ADC);
adc_enable_interrupt(ADC, ADC_ISR_EOC5);
/**
* \brief Handler for ADC interrupt.
*/
void ADC_Handler(void)
{
uint32_t low_threshold;
uint32_t high_threshold;
uint32_t status = adc_get_status(ADC);
/* Read the status to ack the IT */
if ((status & ADC_ISR_COMPE) == ADC_ISR_COMPE) {
/* Get the potentiometer initial value */
pontentiometer_value = adc_get_channel_value( ADC,
ADC_CHANNEL_POTENTIOMETER );
/* Set Window threshold according to the initial values */
low_threshold = pontentiometer_value -
(NB_INTERVALS * (0x1000 / 256));
if (low_threshold > 0xf0000000) {
low_threshold = 0;
}
high_threshold = pontentiometer_value +
(NB_INTERVALS * (0x1000 / 256));
if (high_threshold >= 0x1000) {
high_threshold = 0x1000 - 1;
}
/* Normalize the value 0 -> 255 */
pontentiometer_value
= pontentiometer_value*100 + 1;
ppt_delay_clapse_counter = 0;
/* Setup Threshold*/
adc_set_comparison_window( ADC, low_threshold,
high_threshold);
/* Compare mode, in the window. */
adc_enable_interrupt(ADC, ADC_IER_COMPE);
}
if (status & ADC_ISR_ENDRX) {
/* Start next buffer */
ADC->ADC_RNPR = (uint32_t)
frame_buffer[(adc_buf_ndx + 2) % AUDIO_NB_BUFFER];
ADC->ADC_RNCR = AUDIO_FRAME_SIZE;
adc_buf_ndx = (adc_buf_ndx + 1) % AUDIO_NB_BUFFER;
adc_nb_samples += AUDIO_FRAME_SIZE;
}
}
/**
* \brief Enter sleep mode using WFI instruction.
* Enable interrupt first and then disable it after wake up.
*/
static void enter_asleep(void)
{
while (1) {
puts("Now switching the device into sleep mode...\r");
/* Clear status register. */
adc_get_status(ADC);
/* Enable Compare Interrupt. */
adc_enable_interrupt(ADC, ADC_IER_COMPE);
__WFI();
/* Every time waked up, break out of the loop. */
break;
}
}
/**
* \brief Configure to trigger ADC by PWM Event Line.
*/
static void configure_pwm_trigger(void)
{
/* PWM frequency in Hz. */
#define PWM_FREQUENCY 2
/* Maximum duty cycle value. */
#define MAX_DUTY_CYCLE 1000
/* Enable PWMC peripheral clock. */
pmc_enable_periph_clk(ID_PWM);
/* Disable PWM channel 0. */
pwm_channel_disable(PWM, PWM_CHANNEL_0);
gpio_configure_pin(PIN_PWMC_PWMH0_TRIG, PIN_PWMC_PWMH0_TRIG_FLAG);
/* Set clock A to run at PWM_FREQUENCY * MAX_DUTY_CYCLE (clock B is not used). */
pwm_clock_t pwm_clock_setting = {
.ul_clka = PWM_FREQUENCY * MAX_DUTY_CYCLE,
.ul_clkb = 0,
.ul_mck = sysclk_get_cpu_hz()
};
pwm_init(PWM, &pwm_clock_setting);
/* Configure PWMC for channel 0 (left-aligned). */
pwm_channel_t pwm_trigger_channel = {
.channel = PWM_CHANNEL_0,
.alignment = PWM_ALIGN_LEFT,
.polarity = PWM_LOW,
.ul_prescaler = PWM_CMR_CPRE_CLKA,
.ul_period = MAX_DUTY_CYCLE,
.ul_duty = MAX_DUTY_CYCLE / 2
};
pwm_channel_init(PWM, &pwm_trigger_channel);
pwm_cmp_t pwm_comparison_setting = {
.unit = PWM_CMP_UNIT_0,
.b_enable = true,
.ul_value = MAX_DUTY_CYCLE / 2,
.b_pulse_on_line_0 = true
};
pwm_cmp_init(PWM, &pwm_comparison_setting);
/* Enable PWM channel 0. */
pwm_channel_enable(PWM, PWM_CHANNEL_0);
/* Set PWM Event Line 0 trigger. */
#if SAM3S || SAM3XA || SAM4S
adc_configure_trigger(ADC, ADC_TRIG_PWM_EVENT_LINE_0, 0);
#elif SAM3U
#ifdef ADC_12B
adc12b_configure_trigger(ADC12B, ADC12B_TRIG_PWM_EVENT_LINE_0);
#else
adc_configure_trigger(ADC, ADC_TRIG_PWM_EVENT_LINE_0);
#endif
#endif
}
#endif
/**
* \brief Read converted data through PDC channel.
*
* \param p_adc The pointer of adc peripheral.
* \param p_s_buffer The destination buffer.
* \param ul_size The size of the buffer.
*/
#if SAM3S || SAM3N || SAM3XA || SAM4S || SAM4C
static uint32_t adc_read_buffer(Adc * p_adc, uint16_t * p_s_buffer, uint32_t ul_size)
{
/* Check if the first PDC bank is free. */
if ((p_adc->ADC_RCR == 0) && (p_adc->ADC_RNCR == 0)) {
p_adc->ADC_RPR = (uint32_t) p_s_buffer;
p_adc->ADC_RCR = ul_size;
p_adc->ADC_PTCR = ADC_PTCR_RXTEN;
return 1;
} else { /* Check if the second PDC bank is free. */
if (p_adc->ADC_RNCR == 0) {
p_adc->ADC_RNPR = (uint32_t) p_s_buffer;
p_adc->ADC_RNCR = ul_size;
return 1;
} else {
return 0;
}
}
}
#elif SAM3U
#ifdef ADC_12B
static uint32_t adc12_read_buffer(Adc12b * p_adc, uint16_t * p_s_buffer,
uint32_t ul_size)
{
/* Check if the first PDC bank is free. */
if ((p_adc->ADC12B_RCR == 0) && (p_adc->ADC12B_RNCR == 0)) {
p_adc->ADC12B_RPR = (uint32_t) p_s_buffer;
p_adc->ADC12B_RCR = ul_size;
p_adc->ADC12B_PTCR = ADC12B_PTCR_RXTEN;
return 1;
} else { /* Check if the second PDC bank is free. */
if (p_adc->ADC12B_RNCR == 0) {
p_adc->ADC12B_RNPR = (uint32_t) p_s_buffer;
p_adc->ADC12B_RNCR = ul_size;
return 1;
} else {
return 0;
}
}
}
#else
static uint32_t adc_read_buffer(Adc * p_adc, uint16_t * p_s_buffer, uint32_t ul_size)
{
/* Check if the first PDC bank is free. */
if ((p_adc->ADC_RCR == 0) && (p_adc->ADC_RNCR == 0)) {
p_adc->ADC_RPR = (uint32_t) p_s_buffer;
p_adc->ADC_RCR = ul_size;
p_adc->ADC_PTCR = ADC_PTCR_RXTEN;
return 1;
} else { /* Check if the second PDC bank is free. */
if (p_adc->ADC_RNCR == 0) {
p_adc->ADC_RNPR = (uint32_t) p_s_buffer;
p_adc->ADC_RNCR = ul_size;
return 1;
} else {
return 0;
}
}
}
#endif
#endif
/**
* \brief Start ADC sample.
* Initialize ADC, set clock and timing, and set ADC to given mode.
*/
static void start_adc(void)
{
/* Enable peripheral clock. */
#if SAM3S || SAM3N || SAM3XA || SAM4S || SAM4C
uint32_t i;
pmc_enable_periph_clk(ID_ADC);
#elif SAM3U
#ifdef ADC_12B
pmc_enable_periph_clk(ID_ADC12B);
#else
pmc_enable_periph_clk(ID_ADC);
#endif
#endif
/* Initialize ADC. */
/*
* Formula: ADCClock = MCK / ( (PRESCAL+1) * 2 )
* For example, MCK = 64MHZ, PRESCAL = 4, then:
* ADCClock = 64 / ((4+1) * 2) = 6.4MHz;
*/
#if SAM3S || SAM3N || SAM3XA || SAM4S || SAM4C
/* Formula:
* Startup Time = startup value / ADCClock
* Startup time = 64 / 6.4MHz = 10 us
*/
adc_init(ADC, sysclk_get_cpu_hz(), 6400000, ADC_STARTUP_TIME_4);
#elif SAM3U
#ifdef ADC_12B
/* Formula:
* Startup Time = (startup value + 1) * 8 / ADCClock
* Startup time = (7 + 1) * 8 / 6.4MHz = 10 us
*/
adc12b_init(ADC12B, sysclk_get_cpu_hz(), 6400000, STARTUP_TIME, OFF_MODE_STARTUP_TIME);
#else
/* Formula:
* Startup Time = (startup value + 1) * 8 / ADCClock
* Startup time = (3 + 1) * 8 / 3.2MHz = 10 us
*/
adc_init(ADC, sysclk_get_cpu_hz(), 3200000, STARTUP_TIME);
#endif
#endif
memset((void *)&g_adc_sample_data, 0, sizeof(g_adc_sample_data));
/* Set ADC timing. */
#if SAM3S || SAM3XA || SAM4S
/* Formula:
* Transfer Time = (TRANSFER * 2 + 3) / ADCClock
* Tracking Time = (TRACKTIM + 1) / ADCClock
* Settling Time = settling value / ADCClock
*
* Transfer Time = (1 * 2 + 3) / 6.4MHz = 781 ns
* Tracking Time = (1 + 1) / 6.4MHz = 312 ns
* Settling Time = 3 / 6.4MHz = 469 ns
*/
adc_configure_timing(ADC, TRACKING_TIME, ADC_SETTLING_TIME_3, TRANSFER_PERIOD);
#elif SAM3N || SAM4C
adc_configure_timing(ADC, TRACKING_TIME);
#elif SAM3U
/* Formula:
* Sample & Hold Time = SHTIM/ADCClock
*
* Sample & Hold Time = 6 / 6.4 = 938 ns
*/
#ifdef ADC_12B
adc12b_configure_timing(ADC12B, SAMPLE_HOLD_TIME);
#else
adc_configure_timing(ADC, SAMPLE_HOLD_TIME);
#endif
#endif
#if SAM3S || SAM3N || SAM3XA || SAM4S || SAM4C
/* Enable channel number tag. */
adc_enable_tag(ADC);
/* Enable/disable sequencer. */
if (g_adc_test_mode.uc_sequence_en) {
/* Set user defined channel sequence. */
adc_configure_sequence(ADC, ch_list, 2);
/* Enable sequencer. */
adc_start_sequencer(ADC);
/* Enable channels. */
for (i = 0; i < 2; i++) {
adc_enable_channel(ADC, (enum adc_channel_num_t)i);
}
/* Update channel number. */
g_adc_sample_data.uc_ch_num[0] = ch_list[0];
g_adc_sample_data.uc_ch_num[1] = ch_list[1];
} else {
/* Disable sequencer. */
adc_stop_sequencer(ADC);
/* Enable channels. */
adc_enable_channel(ADC, ADC_CHANNEL_POTENTIOMETER);
#if SAM3S || SAM3XA || SAM4S || SAM4C
adc_enable_channel(ADC, ADC_TEMPERATURE_SENSOR);
#endif
/* Update channel number. */
g_adc_sample_data.uc_ch_num[0] = ADC_CHANNEL_POTENTIOMETER;
#if SAM3S || SAM3XA || SAM4S || SAM4C
g_adc_sample_data.uc_ch_num[1] = ADC_TEMPERATURE_SENSOR;
#else
g_adc_sample_data.uc_ch_num[1] = ADC_CHANNEL_POTENTIOMETER;
#endif
}
#elif SAM3U
#ifdef ADC_12B
adc12b_enable_channel(ADC12B, ADC_CHANNEL_POTENTIOMETER);
#else
adc_enable_channel(ADC, ADC_CHANNEL_POTENTIOMETER);
#endif
g_adc_sample_data.uc_ch_num[0] = ADC_CHANNEL_POTENTIOMETER;
g_adc_sample_data.uc_ch_num[1] = ADC_CHANNEL_POTENTIOMETER;
#endif
#if SAM3S || SAM3XA || SAM4S || SAM4C
/* Enable the temperature sensor. */
adc_enable_ts(ADC);
#endif
/* Set gain and offset (only single ended mode used here). */
#if SAM3S || SAM3XA || SAM4S
adc_disable_anch(ADC); /* Disable analog change. */
#endif
if (g_adc_test_mode.uc_gain_en) {
#if SAM3S || SAM3XA || SAM4S
adc_enable_anch(ADC);
/* gain = 2 */
adc_set_channel_input_gain(ADC, ADC_CHANNEL_POTENTIOMETER, ADC_GAINVALUE_2);
#elif SAM3U
#ifdef ADC_12B
adc12b_set_input_gain(ADC12B, ADC_GAINVALUE_2);
#endif
#endif
} else {
#if SAM3S || SAM3XA || SAM4S
/* gain = 1 */
adc_set_channel_input_gain(ADC, ADC_CHANNEL_POTENTIOMETER, ADC_GAINVALUE_0);
#elif SAM3U
#ifdef ADC_12B
adc12b_set_input_gain(ADC12B, ADC_GAINVALUE_0);
#endif
#endif
}
if (g_adc_test_mode.uc_offset_en) {
#if SAM3S || SAM3XA || SAM4S
adc_enable_anch(ADC);
adc_enable_channel_input_offset(ADC, ADC_CHANNEL_POTENTIOMETER);
#elif SAM3U
#ifdef ADC_12B
adc12b_enable_input_offset(ADC12B);
#endif
#endif
} else {
#if SAM3S || SAM3XA || SAM4S
adc_disable_channel_input_offset(ADC, ADC_CHANNEL_POTENTIOMETER);
#elif SAM3U
#ifdef ADC_12B
adc12b_disable_input_offset(ADC12B);
#endif
#endif
}
/* Set Auto Calibration Mode. */
#if SAM3S8 || SAM3SD8 || SAM4S
if (g_adc_test_mode.uc_auto_calib_en) {
adc_set_calibmode(ADC);
while (1) {
if ((adc_get_status(ADC) & ADC_ISR_EOCAL) ==
ADC_ISR_EOCAL)
break;
}
}
#endif
#if SAM3S8 || SAM4S || SAM3N || SAM3SD8
/* Set power save. */
if (g_adc_test_mode.uc_power_save_en) {
adc_configure_power_save(ADC, 1, 0);
} else {
adc_configure_power_save(ADC, 0, 0);;
}
#elif SAM3U || SAM4C
#ifdef ADC_12B
/* Set power save. */
if (g_adc_test_mode.uc_power_save_en) {
adc12b_configure_power_save(ADC12B, 1, 0);
} else {
adc12b_configure_power_save(ADC12B, 0, 0);;
}
#else
/* Set power save. */
if (g_adc_test_mode.uc_power_save_en) {
adc_configure_power_save(ADC, 1);
} else {
adc_configure_power_save(ADC, 0);;
}
#endif
#endif
#if SAM3S || SAM3N || SAM3XA || SAM4S || SAM4C
/* Transfer with/without PDC. */
if (g_adc_test_mode.uc_pdc_en) {
adc_read_buffer(ADC, g_adc_sample_data.us_value, BUFFER_SIZE);
/* Enable PDC channel interrupt. */
adc_enable_interrupt(ADC, ADC_IER_RXBUFF);
} else {
/* Enable Data ready interrupt. */
adc_enable_interrupt(ADC, ADC_IER_DRDY);
}
/* Enable ADC interrupt. */
NVIC_EnableIRQ(ADC_IRQn);
#elif SAM3U
#ifdef ADC_12B
/* Transfer with/without PDC. */
if (g_adc_test_mode.uc_pdc_en) {
adc12_read_buffer(ADC12B, g_adc_sample_data.us_value, BUFFER_SIZE);
/* Enable PDC channel interrupt. */
adc12b_enable_interrupt(ADC12B, ADC12B_IER_RXBUFF);
} else {
/* Enable Data ready interrupt. */
adc12b_enable_interrupt(ADC12B, ADC12B_IER_DRDY);
}
/* Enable ADC interrupt. */
NVIC_EnableIRQ(ADC12B_IRQn);
#else
/* Transfer with/without PDC. */
if (g_adc_test_mode.uc_pdc_en) {
adc_read_buffer(ADC, g_adc_sample_data.us_value, BUFFER_SIZE);
/* Enable PDC channel interrupt. */
adc_enable_interrupt(ADC, ADC_IER_RXBUFF);
} else {
/* Enable Data ready interrupt. */
adc_enable_interrupt(ADC, ADC_IER_DRDY);
}
/* Enable ADC interrupt. */
NVIC_EnableIRQ(ADC_IRQn);
#endif
#endif
/* Configure trigger mode and start convention. */
switch (g_adc_test_mode.uc_trigger_mode) {
case TRIGGER_MODE_SOFTWARE:
#if SAM3S || SAM3N || SAM3XA || SAM4S || SAM4C
adc_configure_trigger(ADC, ADC_TRIG_SW, 0); /* Disable hardware trigger. */
#elif SAM3U
#ifdef ADC_12B
adc12b_configure_trigger(ADC12B, ADC12B_TRIG_SW);
#else
adc_configure_trigger(ADC, ADC_TRIG_SW);
#endif
#endif
break;
case TRIGGER_MODE_ADTRG:
#if SAM3S || SAM3N || SAM3XA || SAM4S || SAM4C
gpio_configure_pin(PINS_ADC_TRIG, PINS_ADC_TRIG_FLAG);
adc_configure_trigger(ADC, ADC_TRIG_EXT, 0);
#elif SAM3U
#ifdef ADC_12B
gpio_configure_pin(PINS_ADC12B_TRIG, PINS_ADC12B_TRIG_FLAG);
adc12b_configure_trigger(ADC12B, ADC12B_TRIG_EXT);
#else
gpio_configure_pin(PINS_ADC_TRIG, PINS_ADC_TRIG_FLAG);
adc_configure_trigger(ADC, ADC_TRIG_EXT);
#endif
#endif
break;
case TRIGGER_MODE_TIMER:
configure_time_trigger();
break;
#if SAM3S || SAM3U || SAM3XA || SAM4S
case TRIGGER_MODE_PWM:
configure_pwm_trigger();
break;
#endif
#if SAM3S || SAM3N || SAM3XA || SAM4S || SAM4C
case TRIGGER_MODE_FREERUN:
adc_configure_trigger(ADC, ADC_TRIG_SW, 1);
break;
#endif
default:
break;
}
}
/**
* \brief Systick handler.
*/
void SysTick_Handler(void)
{
gs_ul_ms_ticks++;
}
#if SAM3S || SAM3N || SAM3XA || SAM4S || SAM4C
/**
* \brief Interrupt handler for the ADC.
*/
void ADC_Handler(void)
{
uint32_t i;
uint32_t ul_temp;
uint8_t uc_ch_num;
/* With PDC transfer */
if (g_adc_test_mode.uc_pdc_en) {
if ((adc_get_status(ADC) & ADC_ISR_RXBUFF) ==
ADC_ISR_RXBUFF) {
g_adc_sample_data.us_done = ADC_DONE_MASK;
adc_read_buffer(ADC, g_adc_sample_data.us_value, BUFFER_SIZE);
/* Only keep sample value, and discard channel number. */
for (i = 0; i < NUM_CHANNELS; i++) {
g_adc_sample_data.us_value[i] &= ADC_LCDR_LDATA_Msk;
}
}
} else { /* Without PDC transfer */
if ((adc_get_status(ADC) & ADC_ISR_DRDY) ==
ADC_ISR_DRDY) {
ul_temp = adc_get_latest_value(ADC);
for (i = 0; i < NUM_CHANNELS; i++) {
uc_ch_num = (ul_temp & ADC_LCDR_CHNB_Msk) >>
ADC_LCDR_CHNB_Pos;
if (g_adc_sample_data.uc_ch_num[i] == uc_ch_num) {
g_adc_sample_data.us_value[i] =
ul_temp &
ADC_LCDR_LDATA_Msk;
g_adc_sample_data.us_done |= 1 << i;
}
}
}
}
}
/**
* \brief Turn on/off ADC module.
*
* \param on True to start ADC, false to turn off.
*/
static void demo_start_adc(bool on)
{
uint32_t low_threshold, high_threshold;
if (on == true) {
/* Check if already enabled */
if (demo_adc_on) {
return;
}
demo_config_adc();
/* Start TC0 and hardware trigger. */
tc_start(TC0, 1);
/* Get the potentiometer initial value */
pontentiometer_value = adc_get_channel_value(ADC,
ADC_CHANNEL_POTENTIOMETER);
/* Set Window threshold according to the initial values */
low_threshold = pontentiometer_value -
(NB_INTERVALS * (0x1000 / 256));
if (low_threshold > 0xf000000) {
low_threshold = 0;
}
high_threshold = pontentiometer_value +
(NB_INTERVALS * (0x1000 / 256));
if (high_threshold >= 0x1000) {
high_threshold = 0x1000 - 1;
}
pontentiometer_value
= pontentiometer_value*100 + 1;
/* Channel 5 has to be compared. */
adc_set_comparison_channel(ADC, ADC_CHANNEL_POTENTIOMETER);
/* Compare mode, out the window. */
adc_set_comparison_mode(ADC, ADC_EMR_CMPMODE_OUT);
/* Set up Threshold. */
adc_set_comparison_window(ADC, low_threshold,
high_threshold);
/* Enable ADC interrupt. */
NVIC_EnableIRQ(ADC_IRQn);
/* Enable Compare Interrupt. */
adc_enable_interrupt(ADC, ADC_IER_COMPE);
/* Set adc on flag */
demo_adc_on = 1;
/* Reset clapse time */
ppt_delay_clapse_counter = 0;
} else {
tc_stop(TC0, 1);
/* Enable ADC interrupt. */
NVIC_DisableIRQ(ADC_IRQn);
/* Enable Compare Interrupt. */
adc_disable_interrupt(ADC, ADC_IDR_COMPE);
/* Set adc off flag */
demo_adc_on = 0;
}
}
/**
* \brief Test ADCIFE in Differential mode.
*
* \param test Current test case.
*/
static void run_adcife_diff_test(const struct test_case *test)
{
uint32_t timeout = ADC_NUM_OF_ATTEMPTS;
bool conversion_timeout = false;
struct adc_seq_config adc_seq_cfg = {
/* Select Vref for shift cycle */
.zoomrange = ADC_ZOOMRANGE_0,
/* Pad Ground */
.muxneg = ADC_MUXNEG_1,
/* Scaled Vcc, Vcc/10 */
.muxpos = ADC_MUXPOS_2,
/* Enables the internal voltage sources */
.internal = ADC_INTERNAL_3,
/* Disables the ADC gain error reduction */
.gcomp = ADC_GCOMP_DIS,
/* Disables the HWLA mode */
.hwla = ADC_HWLA_DIS,
/* 12-bits resolution */
.res = ADC_RES_12_BIT,
/* Enables the differential mode */
.bipolar = ADC_BIPOLAR_DIFFERENTIAL
};
struct adc_ch_config adc_ch_cfg = {
.seq_cfg = &adc_seq_cfg,
/* Internal Timer Max Counter */
.internal_timer_max_count = 60,
/* Window monitor mode is off */
.window_mode = 0,
.low_threshold = 0,
.high_threshold = 0,
};
adc_ch_set_config(&g_adc_inst, &adc_ch_cfg);
adc_configure_trigger(&g_adc_inst, ADC_TRIG_CON);
adc_configure_gain(&g_adc_inst, ADC_GAIN_1X);
while (!((adc_get_status(&g_adc_inst) & ADCIFE_SR_SEOC) ==
ADCIFE_SR_SEOC)) {
if (!timeout--) {
conversion_timeout = true;
}
}
test_assert_true(test, conversion_timeout == false, "ADCIFE Differential conversion timeout");
/* Because selected channel is positive input, then in differential mode
* the output conversion result will = 2047 + (Vin/Vref)*2047.
*/
test_assert_true(test, adc_get_last_conv_value(&g_adc_inst) > 2047,
"ADCIFE Differential test failed");
}
/**
* \brief Test ADCIFE in internal timer trigger mode,
* which also tests interrupt driven conversions.
*
* \param test Current test case.
*/
static void run_adcife_itimer_trig_test(const struct test_case *test)
{
struct adc_seq_config adc_seq_cfg = {
/* Select Vref for shift cycle */
.zoomrange = ADC_ZOOMRANGE_0,
/* Pad Ground */
.muxneg = ADC_MUXNEG_1,
/* Scaled Vcc, Vcc/10 */
.muxpos = ADC_MUXPOS_2,
/* Enables the internal voltage sources */
.internal = ADC_INTERNAL_3,
/* Disables the ADC gain error reduction */
.gcomp = ADC_GCOMP_DIS,
/* Disables the HWLA mode */
.hwla = ADC_HWLA_DIS,
/* 12-bits resolution */
.res = ADC_RES_12_BIT,
/* Enables the single-ended mode */
.bipolar = ADC_BIPOLAR_SINGLEENDED
};
struct adc_ch_config adc_ch_cfg = {
.seq_cfg = &adc_seq_cfg,
/* Internal Timer Max Counter */
.internal_timer_max_count = 60,
/* Window monitor mode is off */
.window_mode = 0,
.low_threshold = 0,
.high_threshold = 0,
};
adc_ch_set_config(&g_adc_inst, &adc_ch_cfg);
adc_set_callback(&g_adc_inst, ADC_SEQ_SEOC, adcife_set_conv_flag,
ADCIFE_IRQn, 1);
adc_configure_trigger(&g_adc_inst, ADC_TRIG_INTL_TIMER);
adc_configure_gain(&g_adc_inst, ADC_GAIN_1X);
adc_configure_itimer_period(&g_adc_inst,
adc_ch_cfg.internal_timer_max_count);
adc_start_itimer(&g_adc_inst);
delay_ms(100);
test_assert_true(test, g_uc_condone_flag == 1,
"ADCIFE Internal Timer trigger test failed");
}
/* When VDDANA is in MIN value = 2.4V, the equivalent voltage value is
* (2400 * 255) / ((1 << 10) - 1) = 598mv. The relative digital value is
* 598 * 4095 / 1000 = 2449. */
#define DAC_INTERNAL_MIN_VALUE 2449
/* When VDDANA is in MAX value = 3.6V the equivalent voltage value is
* (3600 * 255) / ((1 << 10) - 1) = 897mv. The relative digital value is
* 897 * 4095 / 1000 = 3673. */
#define DAC_INTERNAL_MAX_VALUE 3673
/* When VCC is in MIN value = 1.6V, the equivalent voltage value is
* 1600 / 10 = 160mv. The relative digital value is
* 160 * 4095 / 1000 = 434. */
#define VCC_SCALED_MIN_VALUE 434
/* When VCC is in MAX value = 3.6V, the equivalent voltage value is
* 3600 / 10 = 360mv. The relative digital value is
* 360 * 4095 / 1000 = 1474. */
#define VCC_SCALED_MAX_VALUE 1474
/**
* \brief Test ADCIFE in multiple channel mode.
*
* \param test Current test case.
*/
static void run_adcife_multichannel_test(const struct test_case *test)
{
start_dac();
adc_pdca_set_config(&g_adc_pdca_cfg);
pdca_channel_set_callback(CONFIG_ADC_PDCA_RX_CHANNEL, pdca_transfer_done,
PDCA_0_IRQn, 1, PDCA_IER_TRC);
adc_configure_trigger(&g_adc_inst, ADC_TRIG_CON);
adc_configure_gain(&g_adc_inst, ADC_GAIN_1X);
delay_ms(100);
/* The DAC output voltage value is 823mv, so the equivalent ADC value should be
* 4095 * 823 / 1000 = 3370. The scaled VCC output voltage is 330mv, so the
* equivalent ADC value should be 4095 * 330 / 1000 = 1351. */
test_assert_true(test,
((DAC_INTERNAL_MIN_VALUE < g_adc_sample_data[0] < DAC_INTERNAL_MAX_VALUE)
&& (VCC_SCALED_MIN_VALUE < g_adc_sample_data[1] < VCC_SCALED_MAX_VALUE)),
"ADCIFE Multichannel test failed");
}
/**
* \brief Test ADCIFE in window monitor mode.
*
* \param test Current test case.
*/
static void run_adcife_wm_test(const struct test_case *test)
{
struct adc_seq_config adc_seq_cfg = {
/* Select Vref for shift cycle */
.zoomrange = ADC_ZOOMRANGE_0,
/* Pad Ground */
.muxneg = ADC_MUXNEG_1,
/* Scaled Vcc, Vcc/10 */
.muxpos = ADC_MUXPOS_2,
/* Enables the internal voltage sources */
.internal = ADC_INTERNAL_3,
/* Disables the ADC gain error reduction */
.gcomp = ADC_GCOMP_DIS,
/* Disables the HWLA mode */
.hwla = ADC_HWLA_DIS,
/* 12-bits resolution */
.res = ADC_RES_12_BIT,
/* Enables the single-ended mode */
.bipolar = ADC_BIPOLAR_SINGLEENDED
};
struct adc_ch_config adc_ch_cfg = {
.seq_cfg = &adc_seq_cfg,
/* Internal Timer Max Counter */
.internal_timer_max_count = 60,
/* Window monitor mode is off */
.window_mode = ADC_WM_MODE_3,
/* The equivalent voltage value is 205 * 1000 / 4095 = 50mv. */
.low_threshold = 205,
/* The equivalent voltage value is 2050 * 1000 / 4095 = 500mv. */
.high_threshold = 2050,
};
adc_ch_set_config(&g_adc_inst, &adc_ch_cfg);
adc_configure_trigger(&g_adc_inst, ADC_TRIG_CON);
adc_configure_gain(&g_adc_inst, ADC_GAIN_1X);
adc_set_callback(&g_adc_inst, ADC_WINDOW_MONITOR, adcife_set_wm_flag,
ADCIFE_IRQn, 1);
delay_ms(100);
test_assert_true(test, g_uc_enter_win_flag == 1,
"ADCIFE Inside Window Mode test failed");
/* The teseted channel voltage is outside window */
adc_disable(&g_adc_inst);
g_uc_enter_win_flag = 0;
adc_seq_cfg.muxpos = ADC_MUXPOS_3;
adc_ch_set_config(&g_adc_inst, &adc_ch_cfg);
adc_configure_trigger(&g_adc_inst, ADC_TRIG_CON);
adc_configure_gain(&g_adc_inst, ADC_GAIN_1X);
adc_enable_interrupt(&g_adc_inst, ADC_WINDOW_MONITOR);
delay_ms(100);
test_assert_true(test, g_uc_enter_win_flag == 0,
"ADCIFE Outside Window Mode test failed");
}
/**
* \brief Run ADCIFE driver unit tests.
*/
int main(void)
{
const usart_serial_options_t usart_serial_options = {
.baudrate = CONF_TEST_BAUDRATE,
.charlength = CONF_TEST_CHARLENGTH,
.paritytype = CONF_TEST_PARITY,
.stopbits = CONF_TEST_STOPBITS
};
/* Initialize the system clock and board */
sysclk_init();
board_init();
/* Enable the debug uart */
stdio_serial_init(CONF_TEST_USART, &usart_serial_options);
#if defined(__GNUC__)
setbuf(stdout, NULL);
#endif
/* Define all the test cases */
DEFINE_TEST_CASE(adcife_init_test, NULL, run_adcife_init_test, NULL,
"ADCIFE Initialize test");
DEFINE_TEST_CASE(adcife_diff_test, NULL, run_adcife_diff_test, NULL,
"ADCIFE Differential test");
DEFINE_TEST_CASE(adcife_itmer_trig_test, NULL, run_adcife_itimer_trig_test,
NULL, "ADCIFE Internal Timer trigger test");
DEFINE_TEST_CASE(adcife_multichannel_test, NULL, run_adcife_multichannel_test, NULL,
"ADCIFE Multichannel test");
DEFINE_TEST_CASE(adcife_wm_test, NULL, run_adcife_wm_test,
NULL, "ADCIFE Window Monitor Mode test");
/* Put test case addresses in an array */
DEFINE_TEST_ARRAY(adcife_tests) = {
&adcife_init_test,
&adcife_diff_test,
&adcife_itmer_trig_test,
&adcife_multichannel_test,
&adcife_wm_test,
};
/* Define the test suite */
DEFINE_TEST_SUITE(adcife_suite, adcife_tests,
"SAM ADCIFE driver test suite");
/* Run all tests in the test suite */
test_suite_run(&adcife_suite);
while (1) {
/* Busy-wait forever. */
}
}
/**
* \brief Example entry point.
*
* \return Unused (ANSI-C compatibility).
*/
int main(void)
{
uint8_t c_choice;
int16_t s_adc_value;
int16_t s_dac_value;
int16_t s_threshold = 0;
float f_dac_data;
uint32_t ul_dac_data;
/* Initialize the SAM system. */
sysclk_init();
board_init();
configure_console();
/* Output example information. */
puts(STRING_HEADER);
/* Initialize threshold. */
gs_us_low_threshold = 500;
gs_us_high_threshold = 2000;
struct adc_config adc_cfg = {
/* System clock division factor is 16 */
.prescal = ADC_PRESCAL_DIV16,
/* The APB clock is used */
.clksel = ADC_CLKSEL_APBCLK,
/* Max speed is 150K */
.speed = ADC_SPEED_150K,
/* ADC Reference voltage is 0.625*VCC */
.refsel = ADC_REFSEL_1,
/* Enables the Startup time */
.start_up = CONFIG_ADC_STARTUP
};
struct adc_seq_config adc_seq_cfg = {
/* Select Vref for shift cycle */
.zoomrange = ADC_ZOOMRANGE_0,
/* Pad Ground */
.muxneg = ADC_MUXNEG_1,
/* DAC Internal */
.muxpos = ADC_MUXPOS_3,
/* Enables the internal voltage sources */
.internal = ADC_INTERNAL_3,
/* Disables the ADC gain error reduction */
.gcomp = ADC_GCOMP_DIS,
/* Disables the HWLA mode */
.hwla = ADC_HWLA_DIS,
/* 12-bits resolution */
.res = ADC_RES_12_BIT,
/* Enables the single-ended mode */
.bipolar = ADC_BIPOLAR_SINGLEENDED
};
struct adc_ch_config adc_ch_cfg = {
.seq_cfg = &adc_seq_cfg,
/* Internal Timer Max Counter */
.internal_timer_max_count = 60,
/* Window monitor mode is off */
.window_mode = ADC_WM_MODE_3,
/* The equivalent voltage value is 500 * VOLT_REF / 4095 = 251mv. */
.low_threshold = gs_us_low_threshold,
/* The equivalent voltage value is 2000 * VOLT_REF / 4095 = 1002mv. */
.high_threshold = gs_us_high_threshold,
};
start_dac();
if(adc_init(&g_adc_inst, ADCIFE, &adc_cfg) != STATUS_OK) {
puts("-F- ADC Init Fail!\n\r");
while(1);
}
if(adc_enable(&g_adc_inst) != STATUS_OK) {
puts("-F- ADC Enable Fail!\n\r");
while(1);
}
adc_ch_set_config(&g_adc_inst, &adc_ch_cfg);
adc_configure_trigger(&g_adc_inst, ADC_TRIG_CON);
adc_configure_gain(&g_adc_inst, ADC_GAIN_1X);
adc_set_callback(&g_adc_inst, ADC_WINDOW_MONITOR, adcife_wm_handler,
ADCIFE_IRQn, 1);
/* Display main menu. */
display_menu();
while (1) {
scanf("%c", (char *)&c_choice);
printf("%c\r\n", c_choice);
switch (c_choice) {
case '0':
adc_disable_interrupt(&g_adc_inst, ADC_WINDOW_MONITOR);
printf("DAC output is set to(mv) from 0mv to %dmv: ",
(int32_t)VOLT_REF);
s_dac_value = get_voltage();
puts("\r");
f_dac_data = (float)s_dac_value * DACC_MAX_DATA / VDDANA;
ul_dac_data = f_to_int(f_dac_data);
if (s_dac_value >= 0) {
dacc_write_conversion_data(DACC, ul_dac_data);
}
delay_ms(100);
adc_clear_status(&g_adc_inst, ADCIFE_SCR_WM);
adc_enable_interrupt(&g_adc_inst, ADC_WINDOW_MONITOR);
break;
case '1':
adc_disable_interrupt(&g_adc_inst, ADC_WINDOW_MONITOR);
printf("Low threshold is set to(mv) from 0mv to %dmv: ",
(int32_t)VOLT_REF);
s_threshold = get_voltage();
puts("\r");
if (s_threshold >= 0) {
s_adc_value = s_threshold * MAX_DIGITAL /
VOLT_REF;
adc_configure_wm_threshold(&g_adc_inst,
s_adc_value,
gs_us_high_threshold);
/* Renew low threshold. */
gs_us_low_threshold = s_adc_value;
float f_low_threshold =
(float)gs_us_low_threshold *
VOLT_REF / MAX_DIGITAL;
uint32_t ul_low_threshold =
f_to_int(f_low_threshold);
printf("Setting low threshold to %u mv (reg value to 0x%x ~%d%%)\n\r",
ul_low_threshold, gs_us_low_threshold,
gs_us_low_threshold * 100 / MAX_DIGITAL);
}
adc_clear_status(&g_adc_inst, ADCIFE_SCR_WM);
adc_enable_interrupt(&g_adc_inst, ADC_WINDOW_MONITOR);
break;
case '2':
adc_disable_interrupt(&g_adc_inst, ADC_WINDOW_MONITOR);
printf("High threshold is set to(mv)from 0mv to %dmv:",
(int32_t)VOLT_REF);
s_threshold = get_voltage();
puts("\r");
if (s_threshold >= 0) {
s_adc_value = s_threshold * MAX_DIGITAL /
VOLT_REF;
adc_configure_wm_threshold(&g_adc_inst,
gs_us_low_threshold,
s_adc_value);
/* Renew high threshold. */
gs_us_high_threshold = s_adc_value;
float f_high_threshold =
(float)gs_us_high_threshold *
VOLT_REF / MAX_DIGITAL;
uint32_t ul_high_threshold =
f_to_int(f_high_threshold);
printf("Setting high threshold to %u mv (reg value to 0x%x ~%d%%)\n\r",
ul_high_threshold, gs_us_high_threshold,
gs_us_high_threshold * 100 / MAX_DIGITAL);
}
adc_clear_status(&g_adc_inst, ADCIFE_SCR_WM);
adc_enable_interrupt(&g_adc_inst, ADC_WINDOW_MONITOR);
break;
case '3':
adc_disable_interrupt(&g_adc_inst, ADC_WINDOW_MONITOR);
puts("-a. Above low threshold.\n\r"
"-b. Below high threshold.\n\r"
"-c. In the comparison window.\n\r"
"-d. Out of the comparison window.\n\r"
"-q. Quit the setting.\r");
c_choice = get_wm_mode();
adc_configure_wm_mode(&g_adc_inst, c_choice);
printf("Comparison mode is %c.\n\r", 'a' + c_choice - 1);
adc_clear_status(&g_adc_inst, ADCIFE_SCR_WM);
adc_enable_interrupt(&g_adc_inst, ADC_WINDOW_MONITOR);
break;
case 'm':
display_menu();
break;
case 'i':
display_info();
adc_clear_status(&g_adc_inst, ADCIFE_SCR_WM);
adc_enable_interrupt(&g_adc_inst, ADC_WINDOW_MONITOR);
break;
}
puts("Press \'m\' or \'M\' to display the main menu again!\r");
}
}