/***************************************************************************//**
* @brief adc_pn_mon
*******************************************************************************/
int32_t adc_pn_mon(adc_core core,
enum adc_pn_sel sel)
{
uint8_t index;
uint32_t reg_data;
int32_t pn_errors = 0;
for (index = 0; index < core.no_of_channels; index++) {
adc_write(core, ADC_REG_CHAN_CNTRL(index), ADC_ENABLE);
adc_set_pnsel(core, index, sel);
}
mdelay(1);
for (index = 0; index < core.no_of_channels; index++) {
adc_write(core, ADC_REG_CHAN_STATUS(index), 0xff);
}
mdelay(100);
for (index = 0; index < core.no_of_channels; index++) {
adc_read(core, ADC_REG_CHAN_STATUS(index), ®_data);
if (reg_data != 0) {
pn_errors = -1;
xil_printf("ADC PN Status: %d, %d, 0x%02x!\n", index, sel, reg_data);
}
}
return pn_errors;
}
/***************************************************************************//**
* @brief adc_setup
*******************************************************************************/
int32_t adc_setup(uint32_t adc_addr, uint32_t dma_addr, uint8_t ch_no)
{
uint8_t index;
uint32_t status;
adc_baseaddr = adc_addr;
adc_dmac_baseaddr = dma_addr;
adc_write(ADC_REG_RSTN, 0x00);
adc_write(ADC_REG_RSTN, 0x03);
mdelay(100);
for(index = 0; index < ch_no; index++)
{
adc_write(ADC_REG_CHAN_CNTRL(index), 0x51);
}
adc_read(ADC_REG_STATUS, &status);
if(status == 0x0)
{
xil_printf("ADC Core Status errors.\n\r");
return -1;
}
else
{
xil_printf("ADC Core successfully initialized.\n");
return 0;
}
}
/*
* Notes: for hw channel, config its hardware configuration register and using sw channel to read it.
*/
static int sci_adc_config(struct adc_sample_data *adc)
{
unsigned addr = 0;
unsigned val = 0;
int ret = 0;
BUG_ON(!adc);
BUG_ON(adc->channel_id > ADC_MAX);
val = BIT_CH_IN_MODE(adc->signal_mode);
val |= BIT_CH_SLOW(adc->sample_speed);
val |= BIT_CH_SCALE(adc->scale);
val |= BIT_CH_ID(adc->channel_id);
val |= BIT_CH_DLY_EN(adc->hw_channel_delay ? 1 : 0);
adc_write(val, io_base + ADC_SW_CH_CFG);
if (adc->channel_type > 0) { /*hardware */
adc_write(BIT_HW_CH_DELAY(adc->hw_channel_delay),
io_base + ADC_HW_CH_DELAY);
if (adc->channel_type == 1) { /*slow */
addr = io_base + ADC_SLOW_HW_CHX_CFG(adc->channel_id);
} else {
addr = io_base + ADC_FAST_HW_CHX_CFG(adc->channel_id);
}
adc_write(val, addr);
}
return ret;
}
/***************************************************************************//**
* @brief adc_set_pnsel
*******************************************************************************/
int32_t adc_set_pnsel(adc_core core,
uint8_t channel,
enum adc_pn_sel sel)
{
uint32_t reg;
adc_read(core, ADC_REG_CHAN_CNTRL_3(channel), ®);
reg &= ~ADC_ADC_PN_SEL(~0);
reg |= ADC_ADC_PN_SEL(sel);
adc_write(core, ADC_REG_CHAN_CNTRL_3(channel), reg);
return 0;
}
/***************************************************************************//**
* @brief adc_setup
*******************************************************************************/
int32_t adc_setup(adc_core core)
{
uint8_t index;
uint32_t reg_data;
uint32_t adc_clock;
adc_read(core, ADC_REG_ID, ®_data);
if (reg_data)
core.master = 1;
else
core.master = 0;
adc_write(core, ADC_REG_RSTN, 0);
adc_write(core, ADC_REG_RSTN, ADC_MMCM_RSTN | ADC_RSTN);
for(index = 0; index < core.no_of_channels; index++) {
adc_write(core, ADC_REG_CHAN_CNTRL(index), 0x51);
}
mdelay(100);
adc_read(core, ADC_REG_STATUS, ®_data);
if(reg_data == 0x0) {
xil_printf("ADC Core Status errors.\n");
return -1;
}
adc_read(core, ADC_REG_CLK_FREQ, &adc_clock);
adc_read(core, ADC_REG_CLK_RATIO, ®_data);
adc_clock = (adc_clock * reg_data * 100) + 0x7fff;
adc_clock = adc_clock >> 16;
xil_printf("ADC Core Initialized (%d MHz).\n", adc_clock);
return 0;
}
int main()
{
adc_struct ADC;
adc_struct *HwMon = &ADC;
adc_setup(
HwMon,
AD5324,
SPI0,
7, // nCS
5, // SCK
6 // MOSI
);
// Sawtooth function
while (1)
{
uint16_t i;
for (i=0; i<4095; i++)
{
adc_write(HwMon, ADC_OUT_A, i);
adc_write(HwMon, ADC_OUT_B, i);
adc_write(HwMon, ADC_OUT_C, i);
adc_write(HwMon, ADC_OUT_D, i);
}
for (i=4095; i>0; i--)
{
adc_write(HwMon, ADC_OUT_A, i);
adc_write(HwMon, ADC_OUT_B, i);
adc_write(HwMon, ADC_OUT_C, i);
adc_write(HwMon, ADC_OUT_D, i);
}
}
return 0;
}
/***************************************************************************//**
* @brief adc_init
*******************************************************************************/
void adc_init(struct ad9361_rf_phy *phy)
{
adc_write(phy, ADC_REG_RSTN, 0);
adc_write(phy, ADC_REG_RSTN, ADC_RSTN);
adc_write(phy, ADC_REG_CHAN_CNTRL(0),
ADC_IQCOR_ENB | ADC_FORMAT_SIGNEXT | ADC_FORMAT_ENABLE | ADC_ENABLE);
adc_write(phy, ADC_REG_CHAN_CNTRL(1),
ADC_IQCOR_ENB | ADC_FORMAT_SIGNEXT | ADC_FORMAT_ENABLE | ADC_ENABLE);
adc_st.rx2tx2 = phy->pdata->rx2tx2;
if(adc_st.rx2tx2)
{
adc_write(phy, ADC_REG_CHAN_CNTRL(2),
ADC_IQCOR_ENB | ADC_FORMAT_SIGNEXT | ADC_FORMAT_ENABLE | ADC_ENABLE);
adc_write(phy, ADC_REG_CHAN_CNTRL(3),
ADC_IQCOR_ENB | ADC_FORMAT_SIGNEXT | ADC_FORMAT_ENABLE | ADC_ENABLE);
}
else
{
adc_write(phy, ADC_REG_CHAN_CNTRL(2), 0);
adc_write(phy, ADC_REG_CHAN_CNTRL(3), 0);
}
}
int sci_adc_get_values(struct adc_sample_data *adc)
{
unsigned long flags, hw_flags;
int cnt = 12;
unsigned addr = 0;
unsigned val = 0;
int ret = 0;
int num = 0;
int sample_bits_msk = 0;
int *pbuf = 0;
if (!adc || adc->channel_id > ADC_MAX)
return -EINVAL;
pbuf = adc->pbuf;
if (!pbuf)
return -EINVAL;
num = adc->sample_num;
if (num > ADC_MAX_SAMPLE_NUM)
return -EINVAL;
sci_adc_lock();
sci_adc_config(adc); //configs adc sample.
addr = io_base + ADC_CTL;
val = adc_read(addr);
val &= ~(BIT_ADC_EN | BIT_SW_CH_ON | BIT_ADC_BIT_MODE_MASK);
adc_write(val, addr);
adc_clear_irq();
val = BIT_SW_CH_RUN_NUM(num);
val |= BIT_ADC_EN;
val |= BIT_ADC_BIT_MODE(adc->sample_bits);
val |= BIT_SW_CH_ON;
adc_write(val, addr);
while ((!adc_raw_irqstatus()) && cnt--) {
udelay(50);
}
if (!cnt) {
ret = -1;
WARN_ON(1);
goto Exit;
}
if (adc->sample_bits)
sample_bits_msk = ((1 << 12) - 1); //12
else
sample_bits_msk = ((1 << 10) - 1); //10
while (num--)
*pbuf++ = adc_get_data(sample_bits_msk);
Exit:
val = adc_read(addr);
val &= ~BIT_ADC_EN;
adc_write(val, addr);
sci_adc_unlock();
return ret;
}
/***************************************************************************//**
* @brief axiadc_write
*******************************************************************************/
void axiadc_write(struct axiadc_state *st, unsigned reg, unsigned val)
{
adc_write(st->phy, reg, val);
}
/***************************************************************************//**
* @brief dac_write
*******************************************************************************/
void dac_write(struct ad9361_rf_phy *phy, uint32_t regAddr, uint32_t data)
{
adc_write(phy, regAddr + 0x4000, data);
}
/***************************************************************************//**
* @brief dac_write
*******************************************************************************/
void dac_write(uint32_t regAddr, uint32_t data)
{
adc_write(regAddr + 0x4000, data);
}
