target_ulong helper_inb(CPUX86State *env, uint32_t port)
{
#ifdef CONFIG_USER_ONLY
fprintf(stderr, "inb: port=0x%04x\n", port);
return 0;
#else
return address_space_ldub(&address_space_io, port,
cpu_get_mem_attrs(env), NULL);
#endif
}
static MemTxResult tz_ppc_read(void *opaque, hwaddr addr, uint64_t *pdata,
unsigned size, MemTxAttrs attrs)
{
TZPPCPort *p = opaque;
TZPPC *s = p->ppc;
int n = p - s->port;
AddressSpace *as = &p->downstream_as;
uint64_t data;
MemTxResult res;
if (!tz_ppc_check(s, n, attrs)) {
trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user);
if (s->cfg_sec_resp) {
return MEMTX_ERROR;
} else {
*pdata = 0;
return MEMTX_OK;
}
}
switch (size) {
case 1:
data = address_space_ldub(as, addr, attrs, &res);
break;
case 2:
data = address_space_lduw_le(as, addr, attrs, &res);
break;
case 4:
data = address_space_ldl_le(as, addr, attrs, &res);
break;
case 8:
data = address_space_ldq_le(as, addr, attrs, &res);
break;
default:
g_assert_not_reached();
}
*pdata = data;
return res;
}
static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr,
uint64_t *data, unsigned size,
MemTxAttrs attrs)
{
DinoState *s = opaque;
MemTxResult ret = MEMTX_OK;
AddressSpace *io;
uint16_t ioaddr;
uint32_t val;
switch (addr) {
case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3:
/* Read from PCI IO space. */
io = &address_space_io;
ioaddr = s->parent_obj.config_reg;
switch (size) {
case 1:
val = address_space_ldub(io, ioaddr, attrs, &ret);
break;
case 2:
val = address_space_lduw_be(io, ioaddr, attrs, &ret);
break;
case 4:
val = address_space_ldl_be(io, ioaddr, attrs, &ret);
break;
default:
g_assert_not_reached();
}
break;
case DINO_IO_ADDR_EN:
val = s->io_addr_en;
break;
case DINO_IO_CONTROL:
val = s->io_control;
break;
case DINO_IAR0:
val = s->iar0;
break;
case DINO_IAR1:
val = s->iar1;
break;
case DINO_IMR:
val = s->imr;
break;
case DINO_ICR:
val = s->icr;
break;
case DINO_IPR:
val = s->ipr;
/* Any read to IPR clears the register. */
s->ipr = 0;
break;
case DINO_ILR:
val = s->ilr;
break;
case DINO_IRR0:
val = s->ilr & s->imr & ~s->icr;
break;
case DINO_IRR1:
val = s->ilr & s->imr & s->icr;
break;
default:
/* Controlled by dino_chip_mem_valid above. */
g_assert_not_reached();
}
*data = val;
return ret;
}
