void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
{
#ifdef CONFIG_USER_ONLY
fprintf(stderr, "outb: port=0x%04x, data=%02x\n", port, data);
#else
address_space_stb(&address_space_io, port, data,
cpu_get_mem_attrs(env), NULL);
#endif
}
static int s390_virtio_hcall_reset(const uint64_t *args)
{
uint64_t mem = args[0];
VirtIOS390Device *dev;
dev = s390_virtio_bus_find_mem(s390_bus, mem);
if (dev == NULL) {
return -EINVAL;
}
virtio_reset(dev->vdev);
address_space_stb(&address_space_memory,
dev->dev_offs + VIRTIO_DEV_OFFS_STATUS, 0,
MEMTXATTRS_UNSPECIFIED, NULL);
s390_virtio_device_sync(dev);
s390_virtio_reset_idx(dev);
return 0;
}
static MemTxResult tz_ppc_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size, MemTxAttrs attrs)
{
TZPPCPort *p = opaque;
TZPPC *s = p->ppc;
AddressSpace *as = &p->downstream_as;
int n = p - s->port;
MemTxResult res;
if (!tz_ppc_check(s, n, attrs)) {
trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user);
if (s->cfg_sec_resp) {
return MEMTX_ERROR;
} else {
return MEMTX_OK;
}
}
switch (size) {
case 1:
address_space_stb(as, addr, val, attrs, &res);
break;
case 2:
address_space_stw_le(as, addr, val, attrs, &res);
break;
case 4:
address_space_stl_le(as, addr, val, attrs, &res);
break;
case 8:
address_space_stq_le(as, addr, val, attrs, &res);
break;
default:
g_assert_not_reached();
}
return res;
}
static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr,
uint64_t val, unsigned size,
MemTxAttrs attrs)
{
DinoState *s = opaque;
AddressSpace *io;
MemTxResult ret;
uint16_t ioaddr;
switch (addr) {
case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3:
/* Write into PCI IO space. */
io = &address_space_io;
ioaddr = s->parent_obj.config_reg;
switch (size) {
case 1:
address_space_stb(io, ioaddr, val, attrs, &ret);
break;
case 2:
address_space_stw_be(io, ioaddr, val, attrs, &ret);
break;
case 4:
address_space_stl_be(io, ioaddr, val, attrs, &ret);
break;
default:
g_assert_not_reached();
}
return ret;
case DINO_IO_ADDR_EN:
/* Never allow first (=firmware) and last (=Dino) areas. */
s->io_addr_en = val & 0x7ffffffe;
gsc_to_pci_forwarding(s);
break;
case DINO_IO_CONTROL:
s->io_control = val;
gsc_to_pci_forwarding(s);
break;
case DINO_IAR0:
s->iar0 = val;
break;
case DINO_IAR1:
s->iar1 = val;
break;
case DINO_IMR:
s->imr = val;
break;
case DINO_ICR:
s->icr = val;
break;
case DINO_IPR:
/* Any write to IPR clears the register. */
s->ipr = 0;
break;
case DINO_ILR:
case DINO_IRR0:
case DINO_IRR1:
/* These registers are read-only. */
break;
default:
/* Controlled by dino_chip_mem_valid above. */
g_assert_not_reached();
}
return MEMTX_OK;
}
