void keysetup(riv_context_t* ctx, const unsigned char key[KEYLEN])
{
AES_KEY expanded_sk;
__m128i sk = loadu(key);
__m128i k;
aes_expand_key(sk, expanded_sk);
k = aes_encrypt(zero, expanded_sk);
store(ctx->enc_key, k);
aes_expand_key(k, ctx->expanced_enc_key);
uint8_t prf_key[CLHASH_KEYLEN];
const size_t num_blocks = CLHASH_KEYLEN / BLOCKLEN;
size_t j = 0;
for (size_t i = 1; i <= num_blocks; ++i) {
storeu((prf_key + j), aes_encrypt(
_mm_setr_epi8(i,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0), expanded_sk));
j += BLOCKLEN;
}
clhash_keysetup(&(ctx->prf_context), prf_key);
}
int main() {
uint64_t text[2] = {0};
unsigned char *plaintext_ptr = (unsigned char *)text;
const unsigned char key[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f};
unsigned char expanded_key[176] = {0};
unsigned char ciphertext[16] = {0};
aes_expand_key(key, expanded_key);
#define NUM_LOOPS 10000000
for (int i=0; i < NUM_LOOPS; i++) {
text[1]++;
aes_encrypt_aesni(plaintext_ptr, ciphertext, expanded_key);
// print_hex(ciphertext, 16);
}
return 0;
}
/**
* do_aes() - Handle the "aes" command-line command
* @cmdtp: Command data struct pointer
* @flag: Command flag
* @argc: Command-line argument count
* @argv: Array of command-line arguments
*
* Returns zero on success, CMD_RET_USAGE in case of misuse and negative
* on error.
*/
static int do_aes(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
uint32_t key_addr, iv_addr, src_addr, dst_addr, len;
uint8_t *key_ptr, *iv_ptr, *src_ptr, *dst_ptr;
uint8_t key_exp[AES_EXPAND_KEY_LENGTH];
uint32_t aes_blocks;
int enc;
if (argc != 7)
return CMD_RET_USAGE;
if (!strncmp(argv[1], "enc", 3))
enc = 1;
else if (!strncmp(argv[1], "dec", 3))
enc = 0;
else
return CMD_RET_USAGE;
key_addr = simple_strtoul(argv[2], NULL, 16);
iv_addr = simple_strtoul(argv[3], NULL, 16);
src_addr = simple_strtoul(argv[4], NULL, 16);
dst_addr = simple_strtoul(argv[5], NULL, 16);
len = simple_strtoul(argv[6], NULL, 16);
key_ptr = (uint8_t *)key_addr;
iv_ptr = (uint8_t *)iv_addr;
src_ptr = (uint8_t *)src_addr;
dst_ptr = (uint8_t *)dst_addr;
/* First we expand the key. */
aes_expand_key(key_ptr, key_exp);
/* Calculate the number of AES blocks to encrypt. */
aes_blocks = DIV_ROUND_UP(len, AES_KEY_LENGTH);
if (enc)
aes_cbc_encrypt_blocks(key_exp, iv_ptr, src_ptr, dst_ptr,
aes_blocks);
else
aes_cbc_decrypt_blocks(key_exp, iv_ptr, src_ptr, dst_ptr,
aes_blocks);
return 0;
}
static int env_aes_cbc_crypt(env_t *env, const int enc)
{
unsigned char *data = env->data;
uint8_t *key;
uint8_t key_exp[AES_EXPAND_KEY_LENGTH];
uint32_t aes_blocks;
key = env_aes_cbc_get_key();
if (!key)
return -EINVAL;
/* First we expand the key. */
aes_expand_key(key, key_exp);
/* Calculate the number of AES blocks to encrypt. */
aes_blocks = ENV_SIZE / AES_KEY_LENGTH;
if (enc)
aes_cbc_encrypt_blocks(key_exp, data, data, aes_blocks);
else
aes_cbc_decrypt_blocks(key_exp, data, data, aes_blocks);
return 0;
}
void encripta(void)
{
int bo_0 = 0;
int bo_1 = 0;
int bo_2 = 0;
int bo_3 = 0;
int config = 0;
int i;
int cnt =0;
unsigned int key[4];
int config1, config2, config3, config4, config5, config6, config7, config8, config9, config10;
/* int debug_signal_0 = 0;
int debug_signal_31, debug_signal_32, debug_signal_33, debug_signal_34,debug_signal_35, debug_signal_36, debug_signal_37, debug_signal_38, debug_signal_39;
int debug_signal_1 = 0;
int debug_signal_2 = 0;
int debug_signal_3 = 0;
*/
key[0] = 0x09cf4f3c;
key[1] = 0xabf71588;
key[2] = 0x28aed2a6;
key[3] = 0x2b7e1516;
i = aes_expand_key(key);
xil_printf("i = %d\n\r",i);
/*
xil_printf("Teste: %d %d %d %d %d\n\r", bo_0, bo_1, bo_2, bo_3, config);
// Set config = 1
xil_printf("Inicializando CONFIG\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x10);
// verifica config
xil_printf("\nConferindo Config\n\r");
config = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
xil_printf("Config = %08x \n\r",config);
//printf("Endereço de reg16 é 0x%08x \n",AES_BASEADDR+CONFIG_OFFSET);
// escreve a chave e inicializa KeyExpansion
xil_printf("Escrevendo chave K0\n\r");
Xil_Out32(AES_BASEADDR+BI_E_0_OFFSET,0x09cf4f3c);
Xil_Out32(AES_BASEADDR+BI_E_1_OFFSET,0xabf71588);
Xil_Out32(AES_BASEADDR+BI_E_2_OFFSET,0x28aed2a6);
Xil_Out32(AES_BASEADDR+BI_E_3_OFFSET,0x2b7e1516);
xil_printf("Inicializando Key_Expansion\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x11);
xil_printf("Colocando atraso...\n\r");
//while( config == 0xca10d009 )
xil_printf("\n\rConferindo se Key_Expansion terminou\n\r");
config = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
xil_printf("Config = %08x \n\r",config);
*/
xil_printf("Preparando Encriptação\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x01);
xil_printf("Escrevendo bloco de entrada 0x3243f6a8885a308d313198a2e0370734\n\r");
Xil_Out32(AES_BASEADDR+BI_E_0_OFFSET,0xe0370734);
Xil_Out32(AES_BASEADDR+BI_E_1_OFFSET,0x313198a2);
Xil_Out32(AES_BASEADDR+BI_E_2_OFFSET,0x885a308d);
Xil_Out32(AES_BASEADDR+BI_E_3_OFFSET,0x3243f6a8);
xil_printf("Inicializando Encriptação\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_1_OFFSET,0x01);
config = Xil_In8(AES_BASEADDR+CONFIG_3_OFFSET);
while ( config != 3)
{
config = Xil_In8(AES_BASEADDR+CONFIG_3_OFFSET);
cnt++;
}
xil_printf("contador = %d\n\r",cnt);
config1 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config2 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config3 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config4 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config5 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config6 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config7 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config8 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config9 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config10 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
xil_printf("Config1 = %08x \n\r",config1);
xil_printf("Config2 = %08x \n\r",config2);
xil_printf("Config3 = %08x \n\r",config3);
xil_printf("Config4 = %08x \n\r",config4);
xil_printf("Config5 = %08x \n\r",config5);
xil_printf("Config6 = %08x \n\r",config6);
xil_printf("Config7 = %08x \n\r",config7);
xil_printf("Config8 = %08x \n\r",config8);
xil_printf("Config9 = %08x \n\r",config9);
xil_printf("Config10 = %08x \n\r",config10);
for( i=0; i<2; i++)
{
//xil_printf("Conferindo Sinais Internos\n\r");
//config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);
//xil_printf("Config = %08x \n\r",config);
/* Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_S0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_34 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_35 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_36 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_37 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_38 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_39 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_31);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_32);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_33);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_34);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_35);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_36);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_37);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_38);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_39);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_0);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_1);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_2);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z1);
debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z2);
debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z3);
debug_signal_34 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z4);
debug_signal_35 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
debug_signal_36 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_37 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
debug_signal_38 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_39 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_31);
xil_printf("z1 = %08x __ ___ ___ __\n\r",debug_signal_32);
xil_printf("z2 = %08x __ ___ ___ __\n\r",debug_signal_33);
xil_printf("z3 = %08x __ ___ ___ __\n\r",debug_signal_34);
xil_printf("z4 = %08x __ ___ ___ __\n\r",debug_signal_35);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_36);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_37);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_38);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_39);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_0);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_1);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_2);
//config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("k2 = %08x __ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
//xil_printf("Config = %08x \n\r",config);
*/
xil_printf("Lendo bloco encriptado\n\r");
bo_0 = Xil_In32(AES_BASEADDR+BO_E_0_OFFSET);
bo_1 = Xil_In32(AES_BASEADDR+BO_E_1_OFFSET);
bo_2 = Xil_In32(AES_BASEADDR+BO_E_2_OFFSET);
bo_3 = Xil_In32(AES_BASEADDR+BO_E_3_OFFSET);
xil_printf("Bo_e = %x %x %x %x\n\r",bo_3, bo_2, bo_1, bo_0);
/* xil_printf("Reinicializando Encriptação\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x08);
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x0A);
*/
//xil_printf("-----------------------------------------\n\r");
}
// xil_printf("Preparando Decriptação\n\r");
// Xil_Out8(AES_BASEADDR+CONFIG_1_OFFSET,0x01);
xil_printf("Escrevendo bloco de entrada bo_e\n\r");
Xil_Out32(AES_BASEADDR+BI_D_0_OFFSET,bo_0);
Xil_Out32(AES_BASEADDR+BI_D_1_OFFSET,bo_1);
Xil_Out32(AES_BASEADDR+BI_D_2_OFFSET,bo_2);
Xil_Out32(AES_BASEADDR+BI_D_3_OFFSET,bo_3);
xil_printf("Lendo bloco escrito para decriptação\n\r");
bo_0 = Xil_In32(AES_BASEADDR+BO_D_0_OFFSET);
bo_1 = Xil_In32(AES_BASEADDR+BO_D_1_OFFSET);
bo_2 = Xil_In32(AES_BASEADDR+BO_D_2_OFFSET);
bo_3 = Xil_In32(AES_BASEADDR+BO_D_3_OFFSET);
xil_printf("Bo_e = %x %x %x %x\n\r",bo_3, bo_2, bo_1, bo_0);
xil_printf("Inicializando Decriptação\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_2_OFFSET,0x01);
for( i=0; i<2; i++)
{
//xil_printf("Conferindo Sinais Internos\n\r");
//config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);
//xil_printf("Config = %08x \n\r",config);
/* Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_S0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_34 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_35 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_36 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_37 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_38 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_39 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_31);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_32);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_33);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_34);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_35);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_36);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_37);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_38);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_39);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_0);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_1);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_2);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z1);
debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z2);
debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z3);
debug_signal_34 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z4);
debug_signal_35 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
debug_signal_36 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_37 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
debug_signal_38 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_39 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_31);
xil_printf("z1 = %08x __ ___ ___ __\n\r",debug_signal_32);
xil_printf("z2 = %08x __ ___ ___ __\n\r",debug_signal_33);
xil_printf("z3 = %08x __ ___ ___ __\n\r",debug_signal_34);
xil_printf("z4 = %08x __ ___ ___ __\n\r",debug_signal_35);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_36);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_37);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_38);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_39);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_0);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_1);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_2);
//config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("k2 = %08x __ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
//xil_printf("Config = %08x \n\r",config);
*/
xil_printf("Lendo bloco decriptado\n\r");
bo_0 = Xil_In32(AES_BASEADDR+BO_D_0_OFFSET);
bo_1 = Xil_In32(AES_BASEADDR+BO_D_1_OFFSET);
bo_2 = Xil_In32(AES_BASEADDR+BO_D_2_OFFSET);
bo_3 = Xil_In32(AES_BASEADDR+BO_D_3_OFFSET);
xil_printf("Bo_d = %x %x %x %x\n\r",bo_3, bo_2, bo_1, bo_0);
/* xil_printf("Reinicializando Encriptação\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x08);
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x0A);
*/
//xil_printf("-----------------------------------------\n\r");
}
xil_printf("Lendo config\n\r");
config = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
xil_printf("Config = %8x\n\r",config);
/*
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_S0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_31);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_32);
xil_printf("s0 = %08x __ ___ ___ __\n\r\n\r",debug_signal_33);
xil_printf("Lendo bloco encriptado\n\r");
bo_0 = Xil_In32(AES_BASEADDR+BO_E_0_OFFSET);
bo_1 = Xil_In32(AES_BASEADDR+BO_E_1_OFFSET);
bo_2 = Xil_In32(AES_BASEADDR+BO_E_2_OFFSET);
bo_3 = Xil_In32(AES_BASEADDR+BO_E_3_OFFSET);
xil_printf("Bo = %x %x %x %x\n\r",bo_3, bo_2, bo_1, bo_0);
*/
xil_printf("Done\n\r");
}
