static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) { uint8_t split_status[4]; uint8_t split_status1[4]; uint8_t sg_split_status[2]; uint8_t sg_split_status1[2]; ahd_mode_state saved_modes; u_int i; uint16_t pcix_status; pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS, 2); printf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", ahd_name(ahd), pcix_status); saved_modes = ahd_save_modes(ahd); for (i = 0; i < 4; i++) { ahd_set_modes(ahd, i, i); split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); if (i > 1) continue; sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); } for (i = 0; i < 4; i++) { u_int bit; for (bit = 0; bit < 8; bit++) { if ((split_status[i] & (0x1 << bit)) != 0) { static const char *s; s = split_status_strings[bit]; printf(s, ahd_name(ahd), split_status_source[i]); } if (i > 1) continue; if ((sg_split_status[i] & (0x1 << bit)) != 0) { static const char *s; s = split_status_strings[bit]; printf(s, ahd_name(ahd), "SG"); } } } ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS, pcix_status, 2); ahd_outb(ahd, CLRINT, CLRSPLTINT); ahd_restore_modes(ahd, saved_modes); }
int ahd_pci_test_register_access(struct ahd_softc *ahd) { uint32_t cmd; u_int targpcistat; u_int pci_status1; int error; uint8_t hcntrl; error = EIO; cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, 2); ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd & ~PCIM_CMD_SERRESPEN, 2); hcntrl = ahd_inb(ahd, HCNTRL); if (hcntrl == 0xFF) goto fail; hcntrl &= ~CHIPRST; ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); while (ahd_is_paused(ahd) == 0) ; ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); targpcistat = ahd_inb(ahd, TARGPCISTAT); ahd_outb(ahd, TARGPCISTAT, targpcistat); pci_status1 = ahd_pci_read_config(ahd->dev_softc, PCIR_STATUS + 1, 1); ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, pci_status1, 1); ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); ahd_outb(ahd, CLRINT, CLRPCIINT); ahd_outb(ahd, SEQCTL0, PERRORDIS); ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) goto fail; if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); targpcistat = ahd_inb(ahd, TARGPCISTAT); if ((targpcistat & STA) != 0) goto fail; } error = 0; fail: if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); targpcistat = ahd_inb(ahd, TARGPCISTAT); ahd_outb(ahd, TARGPCISTAT, targpcistat); pci_status1 = ahd_pci_read_config(ahd->dev_softc, PCIR_STATUS + 1, 1); ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, pci_status1, 1); ahd_outb(ahd, CLRINT, CLRPCIINT); } ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, 2); return (error); }
static void ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control) { int error; u_int sxfrctl1; uint8_t termctl; uint32_t devconfig; devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, 4); devconfig &= ~STPWLEVEL; if ((ahd->flags & AHD_STPWLEVEL_A) != 0) devconfig |= STPWLEVEL; if (bootverbose) printf("%s: STPWLEVEL is %s\n", ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off"); ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, 4); if ((ahd->flags & AHD_CURRENT_SENSING) != 0) { (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0); } error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl); if ((adapter_control & CFAUTOTERM) == 0) { if (bootverbose) printf("%s: Manual Primary Termination\n", ahd_name(ahd)); termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH); if ((adapter_control & CFSTERM) != 0) termctl |= FLX_TERMCTL_ENPRILOW; if ((adapter_control & CFWSTERM) != 0) termctl |= FLX_TERMCTL_ENPRIHIGH; } else if (error != 0) { printf("%s: Primary Auto-Term Sensing failed! " "Using Defaults.\n", ahd_name(ahd)); termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH; } if ((adapter_control & CFSEAUTOTERM) == 0) { if (bootverbose) printf("%s: Manual Secondary Termination\n", ahd_name(ahd)); termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH); if ((adapter_control & CFSELOWTERM) != 0) termctl |= FLX_TERMCTL_ENSECLOW; if ((adapter_control & CFSEHIGHTERM) != 0) termctl |= FLX_TERMCTL_ENSECHIGH; } else if (error != 0) { printf("%s: Secondary Auto-Term Sensing failed! " "Using Defaults.\n", ahd_name(ahd)); termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH; } sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN; ahd->flags &= ~AHD_TERM_ENB_A; if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) { ahd->flags |= AHD_TERM_ENB_A; sxfrctl1 |= STPWEN; } ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN); ahd_outb(ahd, SXFRCTL1, sxfrctl1); error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl); if (error != 0) { printf("%s: Unable to set termination settings!\n", ahd_name(ahd)); } else if (bootverbose) { printf("%s: Primary High byte termination %sabled\n", ahd_name(ahd), (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis"); printf("%s: Primary Low byte termination %sabled\n", ahd_name(ahd), (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis"); printf("%s: Secondary High byte termination %sabled\n", ahd_name(ahd), (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis"); printf("%s: Secondary Low byte termination %sabled\n", ahd_name(ahd), (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis"); } return; }
static int ahd_aic790X_setup(struct ahd_softc *ahd) { ahd_dev_softc_t pci; u_int rev; pci = ahd->dev_softc; rev = ahd_pci_read_config(pci, PCIR_REVID, /*bytes*/1); if (rev < ID_AIC7902_PCI_REV_A4) { printk("%s: Unable to attach to unsupported chip revision %d\n", ahd_name(ahd), rev); ahd_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2); return (ENXIO); } ahd->channel = ahd_get_pci_function(pci) + 'A'; if (rev < ID_AIC7902_PCI_REV_B0) { /* * Enable A series workarounds. */ ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG | AHD_FAINT_LED_BUG; /* * IO Cell parameter setup. */ AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); if ((ahd->flags & AHD_HP_BOARD) == 0) AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); } else { /* This is revision B and newer. */ extern uint32_t aic79xx_slowcrc; u_int devconfig1; ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY | AHD_BUSFREEREV_BUG; ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; /* If the user requested that the SLOWCRC bit to be set. */ if (aic79xx_slowcrc) ahd->features |= AHD_AIC79XXB_SLOWCRC; /* * Some issues have been resolved in the 7901B. */ if ((ahd->features & AHD_MULTI_FUNC) != 0) ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; /* * IO Cell parameter setup. */ AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); /* * Set the PREQDIS bit for H2B which disables some workaround * that doesn't work on regular PCI busses. * XXX - Find out exactly what this does from the hardware * folks! */ devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); ahd_pci_write_config(pci, DEVCONFIG1, devconfig1|PREQDIS, /*bytes*/1); devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /*bytes*/1); } return (0); }
int ahd_pci_config(struct ahd_softc *ahd, const struct ahd_pci_identity *entry) { struct scb_data *shared_scb_data; u_int command; uint32_t devconfig; uint16_t subvendor; int error; shared_scb_data = NULL; ahd->description = entry->name; subvendor = ahd_pci_read_config(ahd->dev_softc, PCIR_SUBVEND_0, 2); if (subvendor == SUBID_HP) ahd->flags |= AHD_HP_BOARD; error = entry->setup(ahd); if (error != 0) return (error); devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, 4); if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { ahd->chip |= AHD_PCI; ahd->bugs &= ~AHD_PCIX_BUG_MASK; } else { ahd->chip |= AHD_PCIX; } ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; ahd_power_state_change(ahd, AHD_POWER_STATE_D0); error = ahd_pci_map_registers(ahd); if (error != 0) return (error); if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { if (bootverbose) printf("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, 4); devconfig |= DACEN; ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, 4); } command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, 2); command |= PCIM_CMD_BUSMASTEREN; ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, 2); error = ahd_softc_init(ahd); if (error != 0) return (error); ahd->bus_intr = ahd_pci_intr; error = ahd_reset(ahd, FALSE); if (error != 0) return (ENXIO); ahd->pci_cachesize = ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, 1) & CACHESIZE; ahd->pci_cachesize *= 4; ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); error = ahd_check_extport(ahd); if (error != 0) return (error); error = ahd_init(ahd); if (error != 0) return (error); ahd->init_level++; return ahd_pci_map_int(ahd); }
static void ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat) { uint8_t split_status[4]; uint8_t split_status1[4]; uint8_t sg_split_status[2]; uint8_t sg_split_status1[2]; ahd_mode_state saved_modes; u_int i; uint16_t pcix_status; /* * Check for splits in all modes. Modes 0 and 1 * additionally have SG engine splits to look at. */ pcix_status = ahd_pci_read_config(ahd->dev_softc, PCIXR_STATUS, /*bytes*/2); printk("%s: PCI Split Interrupt - PCI-X status = 0x%x\n", ahd_name(ahd), pcix_status); saved_modes = ahd_save_modes(ahd); for (i = 0; i < 4; i++) { ahd_set_modes(ahd, i, i); split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0); split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1); /* Clear latched errors. So our interrupt deasserts. */ ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]); ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]); if (i > 1) continue; sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0); sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1); /* Clear latched errors. So our interrupt deasserts. */ ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]); ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]); } for (i = 0; i < 4; i++) { u_int bit; for (bit = 0; bit < 8; bit++) { if ((split_status[i] & (0x1 << bit)) != 0) { static const char *s; s = split_status_strings[bit]; printk(s, ahd_name(ahd), split_status_source[i]); } if (i > 1) continue; if ((sg_split_status[i] & (0x1 << bit)) != 0) { static const char *s; s = split_status_strings[bit]; printk(s, ahd_name(ahd), "SG"); } } } /* * Clear PCI-X status bits. */ ahd_pci_write_config(ahd->dev_softc, PCIXR_STATUS, pcix_status, /*bytes*/2); ahd_outb(ahd, CLRINT, CLRSPLTINT); ahd_restore_modes(ahd, saved_modes); }
/* * Perform some simple tests that should catch situations where * our registers are invalidly mapped. */ int ahd_pci_test_register_access(struct ahd_softc *ahd) { uint32_t cmd; u_int targpcistat; u_int pci_status1; int error; uint8_t hcntrl; error = EIO; /* * Enable PCI error interrupt status, but suppress NMIs * generated by SERR raised due to target aborts. */ cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); /* * First a simple test to see if any * registers can be read. Reading * HCNTRL has no side effects and has * at least one bit that is guaranteed to * be zero so it is a good register to * use for this test. */ hcntrl = ahd_inb(ahd, HCNTRL); if (hcntrl == 0xFF) goto fail; /* * Next create a situation where write combining * or read prefetching could be initiated by the * CPU or host bridge. Our device does not support * either, so look for data corruption and/or flaged * PCI errors. First pause without causing another * chip reset. */ hcntrl &= ~CHIPRST; ahd_outb(ahd, HCNTRL, hcntrl|PAUSE); while (ahd_is_paused(ahd) == 0) ; /* Clear any PCI errors that occurred before our driver attached. */ ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); targpcistat = ahd_inb(ahd, TARGPCISTAT); ahd_outb(ahd, TARGPCISTAT, targpcistat); pci_status1 = ahd_pci_read_config(ahd->dev_softc, PCIR_STATUS + 1, /*bytes*/1); ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, pci_status1, /*bytes*/1); ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); ahd_outb(ahd, CLRINT, CLRPCIINT); ahd_outb(ahd, SEQCTL0, PERRORDIS); ahd_outl(ahd, SRAM_BASE, 0x5aa555aa); if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa) goto fail; if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); targpcistat = ahd_inb(ahd, TARGPCISTAT); if ((targpcistat & STA) != 0) goto fail; } error = 0; fail: if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) { ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG); targpcistat = ahd_inb(ahd, TARGPCISTAT); /* Silently clear any latched errors. */ ahd_outb(ahd, TARGPCISTAT, targpcistat); pci_status1 = ahd_pci_read_config(ahd->dev_softc, PCIR_STATUS + 1, /*bytes*/1); ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1, pci_status1, /*bytes*/1); ahd_outb(ahd, CLRINT, CLRPCIINT); } ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS); ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); return (error); }
int ahd_pci_config(struct ahd_softc *ahd, const struct ahd_pci_identity *entry) { struct scb_data *shared_scb_data; u_int command; uint32_t devconfig; uint16_t subvendor; int error; shared_scb_data = NULL; ahd->description = entry->name; /* * Record if this is an HP board. */ subvendor = ahd_pci_read_config(ahd->dev_softc, PCIR_SUBVEND_0, /*bytes*/2); if (subvendor == SUBID_HP) ahd->flags |= AHD_HP_BOARD; error = entry->setup(ahd); if (error != 0) return (error); devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) { ahd->chip |= AHD_PCI; /* Disable PCIX workarounds when running in PCI mode. */ ahd->bugs &= ~AHD_PCIX_BUG_MASK; } else { ahd->chip |= AHD_PCIX; } ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)]; ahd_power_state_change(ahd, AHD_POWER_STATE_D0); error = ahd_pci_map_registers(ahd); if (error != 0) return (error); /* * If we need to support high memory, enable dual * address cycles. This bit must be set to enable * high address bit generation even if we are on a * 64bit bus (PCI64BIT set in devconfig). */ if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) { if (bootverbose) printk("%s: Enabling 39Bit Addressing\n", ahd_name(ahd)); devconfig = ahd_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4); devconfig |= DACEN; ahd_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); } /* Ensure busmastering is enabled */ command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2); command |= PCIM_CMD_BUSMASTEREN; ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2); error = ahd_softc_init(ahd); if (error != 0) return (error); ahd->bus_intr = ahd_pci_intr; error = ahd_reset(ahd, /*reinit*/FALSE); if (error != 0) return (ENXIO); ahd->pci_cachesize = ahd_pci_read_config(ahd->dev_softc, CSIZE_LATTIME, /*bytes*/1) & CACHESIZE; ahd->pci_cachesize *= 4; ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI); /* See if we have a SEEPROM and perform auto-term */ error = ahd_check_extport(ahd); if (error != 0) return (error); /* Core initialization */ error = ahd_init(ahd); if (error != 0) return (error); ahd->init_level++; /* * Allow interrupts now that we are completely setup. */ return ahd_pci_map_int(ahd); }
static int ahd_aic790X_setup(struct ahd_softc *ahd) { ahd_dev_softc_t pci; u_int rev; pci = ahd->dev_softc; rev = ahd_pci_read_config(pci, PCIR_REVID, /* */1); if (rev < ID_AIC7902_PCI_REV_A4) { printk("%s: Unable to attach to unsupported chip revision %d\n", ahd_name(ahd), rev); ahd_pci_write_config(pci, PCIR_COMMAND, 0, /* */2); return (ENXIO); } ahd->channel = ahd_get_pci_function(pci) + 'A'; if (rev < ID_AIC7902_PCI_REV_B0) { /* */ ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG | AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG | AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG | AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG | AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG | AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG | AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG | AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG | AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG | AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG | AHD_FAINT_LED_BUG; /* */ AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); if ((ahd->flags & AHD_HP_BOARD) == 0) AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA); } else { /* */ extern uint32_t aic79xx_slowcrc; u_int devconfig1; ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS | AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY | AHD_BUSFREEREV_BUG; ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG; /* */ if (aic79xx_slowcrc) ahd->features |= AHD_AIC79XXB_SLOWCRC; /* */ if ((ahd->features & AHD_MULTI_FUNC) != 0) ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG; /* */ AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29); AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB); AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF); /* */ devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /* */1); ahd_pci_write_config(pci, DEVCONFIG1, devconfig1|PREQDIS, /* */1); devconfig1 = ahd_pci_read_config(pci, DEVCONFIG1, /* */1); } return (0); }
int ahd_pci_map_registers(struct ahd_softc *ahd) { uint32_t command; resource_size_t base; uint8_t __iomem *maddr; int error; /* * If its allowed, we prefer memory mapped access. */ command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, 4); command &= ~(PCIM_CMD_PORTEN|PCIM_CMD_MEMEN); base = 0; maddr = NULL; error = ahd_linux_pci_reserve_mem_region(ahd, &base, &maddr); if (error == 0) { ahd->platform_data->mem_busaddr = base; ahd->tags[0] = BUS_SPACE_MEMIO; ahd->bshs[0].maddr = maddr; ahd->tags[1] = BUS_SPACE_MEMIO; ahd->bshs[1].maddr = maddr + 0x100; ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command | PCIM_CMD_MEMEN, 4); if (ahd_pci_test_register_access(ahd) != 0) { printf("aic79xx: PCI Device %d:%d:%d " "failed memory mapped test. Using PIO.\n", ahd_get_pci_bus(ahd->dev_softc), ahd_get_pci_slot(ahd->dev_softc), ahd_get_pci_function(ahd->dev_softc)); iounmap(maddr); release_mem_region(ahd->platform_data->mem_busaddr, 0x1000); ahd->bshs[0].maddr = NULL; maddr = NULL; } else command |= PCIM_CMD_MEMEN; } else if (bootverbose) { printf("aic79xx: PCI%d:%d:%d MEM region 0x%llx " "unavailable. Cannot memory map device.\n", ahd_get_pci_bus(ahd->dev_softc), ahd_get_pci_slot(ahd->dev_softc), ahd_get_pci_function(ahd->dev_softc), (unsigned long long)base); } if (maddr == NULL) { resource_size_t base2; error = ahd_linux_pci_reserve_io_regions(ahd, &base, &base2); if (error == 0) { ahd->tags[0] = BUS_SPACE_PIO; ahd->tags[1] = BUS_SPACE_PIO; ahd->bshs[0].ioport = (u_long)base; ahd->bshs[1].ioport = (u_long)base2; command |= PCIM_CMD_PORTEN; } else { printf("aic79xx: PCI%d:%d:%d IO regions 0x%llx and " "0x%llx unavailable. Cannot map device.\n", ahd_get_pci_bus(ahd->dev_softc), ahd_get_pci_slot(ahd->dev_softc), ahd_get_pci_function(ahd->dev_softc), (unsigned long long)base, (unsigned long long)base2); } } ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, 4); return (error); }