static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax) { u32 min_mask = 0, max_mask = 0; uint rsrcs; /* */ rsrcs = (ai_get_pmucaps(sih) & PCAP_RC_MASK) >> PCAP_RC_SHIFT; /* */ switch (ai_get_chip_id(sih)) { case BCM43224_CHIP_ID: case BCM43225_CHIP_ID: /* */ break; case BCM4313_CHIP_ID: min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) | PMURES_BIT(RES4313_XTAL_PU_RSRC) | PMURES_BIT(RES4313_ALP_AVAIL_RSRC) | PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC); max_mask = 0xffff; break; default: break; } *pmin = min_mask; *pmax = max_mask; }
u16 si_pmu_fast_pwrup_delay(struct si_pub *sih) { uint delay = PMU_MAX_TRANSITION_DLY; switch (ai_get_chip_id(sih)) { case BCM43224_CHIP_ID: case BCM43225_CHIP_ID: case BCM4313_CHIP_ID: delay = 3700; break; default: break; } return (u16) delay; }
/* query alp/xtal clock frequency */ u32 si_pmu_alp_clock(struct si_pub *sih) { u32 clock = ALP_CLOCK; /* bail out with default */ if (!(ai_get_cccaps(sih) & CC_CAP_PMU)) return clock; switch (ai_get_chip_id(sih)) { case BCM43224_CHIP_ID: case BCM43225_CHIP_ID: case BCM4313_CHIP_ID: /* always 20Mhz */ clock = 20000 * 1000; break; default: break; } return clock; }
void si_pmu_spuravoid_pllupdate(struct si_pub *sih, u8 spuravoid) { u32 tmp = 0; struct bcma_device *core; /* */ core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0); switch (ai_get_chip_id(sih)) { case BCM43224_CHIP_ID: case BCM43225_CHIP_ID: if (spuravoid == 1) { bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL0); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x11500010); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL1); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x000C0C06); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL2); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x0F600a08); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL3); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x00000000); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL4); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x2001E920); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL5); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x88888815); } else { bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL0); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x11100010); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL1); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x000c0c06); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL2); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x03000a08); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL3); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x00000000); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL4); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x200005c0); bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr), PMU1_PLL0_PLLCTL5); bcma_write32(core, CHIPCREGOFFS(pllcontrol_data), 0x88888815); } tmp = 1 << 10; break; default: /* */ return; } bcma_set32(core, CHIPCREGOFFS(pmucontrol), tmp); }