device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled)
{
struct device_path cpu_path;
device_t cpu;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = apic_id;
/* Update CPU in devicetree. */
if (enabled)
cpu = alloc_find_dev(cpu_bus, &cpu_path);
else
cpu = find_dev_path(cpu_bus, &cpu_path);
if (!cpu)
return NULL;
cpu->enabled = enabled;
printk(BIOS_DEBUG, "CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled");
return cpu;
}
void initialize_cpus(struct bus *cpu_bus)
{
struct device_path cpu_path;
struct cpu_info *info;
/* Find the info struct for this CPU */
info = cpu_info();
if (need_lapic_init()) {
/* Ensure the local APIC is enabled */
enable_lapic();
/* Get the device path of the boot CPU */
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = lapicid();
} else {
/* Get the device path of the boot CPU */
cpu_path.type = DEVICE_PATH_CPU;
cpu_path.cpu.id = 0;
}
/* Find the device structure for the boot CPU */
info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
// why here? In case some day we can start core1 in amd_sibling_init
if (is_smp_boot())
copy_secondary_start_to_lowest_1M();
if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION))
smm_init();
/* start all aps at first, so we can init ECC all together */
if (is_smp_boot() && IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
start_other_cpus(cpu_bus, info->cpu);
/* Initialize the bootstrap processor */
cpu_initialize(0);
if (is_smp_boot() && !IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)) {
start_other_cpus(cpu_bus, info->cpu);
/* Now wait the rest of the cpus stop*/
wait_other_cpus_stop(cpu_bus);
}
if (IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) {
/* At this point, all APs are sleeping:
* smm_init() will queue a pending SMI on all cpus
* and smm_other_cpus() will start them one by one */
smm_init();
if (is_smp_boot()) {
last_cpu_index = 0;
smm_other_cpus(cpu_bus, info->cpu);
}
}
smm_init_completion();
if (is_smp_boot())
recover_lowest_1M();
}
