/******************************************************************************** * This program demonstrates use of the Ethernet in the DE2i-150 board. ********************************************************************************/ int main(void){ // Open the sgdma transmit device sgdma_tx_dev = alt_avalon_sgdma_open ("/dev/sgdma_tx"); if (sgdma_tx_dev == NULL) { alt_printf ("Error: could not open scatter-gather dma transmit device\n"); //return -1; } else alt_printf ("Opened scatter-gather dma transmit device\n"); // Open the sgdma receive device sgdma_rx_dev = alt_avalon_sgdma_open ("/dev/sgdma_rx"); if (sgdma_rx_dev == NULL) { alt_printf ("Error: could not open scatter-gather dma receive device\n"); //return -1; } else alt_printf ("Opened scatter-gather dma receive device\n"); // Set interrupts for the sgdma receive device alt_avalon_sgdma_register_callback( sgdma_rx_dev, (alt_avalon_sgdma_callback) rx_ethernet_isr, 0x00000014, NULL ); // Create sgdma receive descriptor alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor, &rx_descriptor_end, (alt_u32 *)rx_frame, 0, 0 ); // Set up non-blocking transfer of sgdma receive descriptor alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor ); // Triple-speed Ethernet MegaCore base address volatile int * tse = (int *) TSE_BASE; // Specify the addresses of the PHY devices to be accessed through MDIO interface *(tse + 0x0F) = 0x10; // Disable read and write transfers and wait *(tse + 0x02) = *(tse + 0x02) | 0x00800220; while ( *(tse + 0x02) != ( *(tse + 0x02) | 0x00800220 ) ); //MAC FIFO Configuration *(tse + 0x09 ) = TSE_TRANSMIT_FIFO_DEPTH-16; *(tse + 0x0E ) = 3; *(tse + 0x0D ) = 8; *(tse + 0x07 ) =TSE_RECEIVE_FIFO_DEPTH-16; *(tse + 0x0C ) = 8; *(tse + 0x0B ) = 8; *(tse + 0x0A ) = 0; *(tse + 0x08 ) = 0; // Initialize the MAC address *(tse + 0x03) = 0x17231C00; *(tse + 0x04) = 0x0000CB4A; // MAC function configuration *(tse + 0x05) = 1518; *(tse + 0x17) = 12; *(tse + 0x06) = 0xFFFF; *(tse + 0x02) = 0x00800220; // Software reset the PHY chip and wait *(tse + 0x02) = 0x00802220; while ( *(tse + 0x02) != ( 0x00800220 ) ) alt_printf( "Hi" ); // Enable read and write transfers, gigabit Ethernet operation and promiscuous mode *(tse + 0x02) = *(tse + 0x02) | 0x0080023B; while ( *(tse + 0x02) != ( *(tse + 0x02) | 0x0080023B ) ) ; while (1) { print=in; in= IORD_ALTERA_AVALON_PIO_DATA(SWITCH_BASE); //read the input from the switch IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE, in); //switch on or switch off the LED if (in==1){ if (print != in){ IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE, 0x0100); alt_printf( "Switch on LED \n" ); } } else{ if (print != in) { IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE, 0x0000); alt_printf( "Switch off LED \n" ); } } } return 0; }
int main (int argc, char* argv[], char* envp[]) { static struct ip_addr ip_zero = { 0 }; /* * Deklaracja adresu MAC w netif( dla wersji z uzyciem pelnego lwIP) */ TSE1netif.hwaddr[0] = 0x11; TSE1netif.hwaddr[1] = 0x6E; TSE1netif.hwaddr[2] = 0x60; TSE1netif.hwaddr[3] = 0x01; TSE1netif.hwaddr[4] = 0x0F; TSE1netif.hwaddr[5] = 0x02; printf("Rozpoczecie dzialania programu\n"); //Otworzenie SGDMA transmitujacego dane do TSE0 sgdma_tx_dev = alt_avalon_sgdma_open ("/dev/sgdma_tx"); if (sgdma_tx_dev == NULL) { printf ("Error: nie mozna otworzyc scatter-gather dma transmit device dla TSE0\n"); return -1; } else printf ("Otworzono scatter-gather dma transmit device dla TSE0\n"); //Otworzenie SGDMA odbierajacego dane z TSE0 sgdma_rx_dev = alt_avalon_sgdma_open ("/dev/sgdma_rx"); if (sgdma_rx_dev == NULL) { printf ("Error: nie mozna otworzyc scatter-gather dma receive device dla TSE0\n"); return -1; } else printf ("Otworzno scatter-gather dma receive device dla TSE0\n"); printf ("System uruchomiony\n"); //Zarejestrowanie wywo³ywania funkcji przy odebraniu danych z TSE0 alt_avalon_sgdma_register_callback( sgdma_rx_dev, (alt_avalon_sgdma_callback) rx_ethernet_isr, 0x00000014, NULL ); // Utworzenie odbiorczego deskryptora sgdma alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor, &rx_descriptor_end, (alt_u32 *)rx_frame, 0, 0 ); // Uruchomienie wykonywania nie blokuj¹cego zapisu z SGDMA TSE0 alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor ); //Otworzenie SGDMA transmitujacego dane do TSE1 alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev1, &rx_descriptor1 ); sgdma_tx_dev1 = alt_avalon_sgdma_open ("/dev/sgdma_tx1"); if (sgdma_tx_dev1 == NULL) { printf ("Error: nie mozna otworzyc scatter-gather dma transmit device dla TSE1\n"); return -1; } else printf ("Otworzono scatter-gather dma transmit device dla TSE1\n"); //Otworzenie SGDMA odbierajacego dane z TSE1 sgdma_rx_dev1 = alt_avalon_sgdma_open ("/dev/sgdma_rx1"); if (sgdma_rx_dev1 == NULL) { printf ("Error: nie mozna otworzyc scatter-gather dma receive device dla TSE1\n"); return -1; } else printf ("Otworzno scatter-gather dma receive device dla TSE1\n"); printf ("System uruchomiony\n"); //Zarejestrowanie wywo³ywania funkcji przy odebraniu danych z TSE1 alt_avalon_sgdma_register_callback( sgdma_rx_dev1, (alt_avalon_sgdma_callback) rx_ethernet_isr1, 0x00000014, NULL ); //// Utworzenie odbiorczego deskryptora sgdma alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor1, &rx_descriptor_end1,(alt_u32 *) rx_frame1, 0, 0 ); // Uruchomienie wykonywania nie blokuj¹cego zapisu z SGDMA TSE1 alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev1, &rx_descriptor1 ); //Utworzenie SGDMA dla szyfratora potokowego Triple DES sgdma_out_dev = alt_avalon_sgdma_open ("/dev/sgdma_3des_out"); if (sgdma_out_dev == NULL) { printf ("Error: nie mozna otworzyc scatter-gather dma odbieraj¹cego zaszyfrowane dane 3DES\n"); return -1; } else printf ("Otworzono scatter-gather dma source-sink odberaj¹cy zaszyfrowane dane z szyfratora 3DES\n"); sgdma_in_dev = alt_avalon_sgdma_open ("/dev/sgdma_3des_in"); if (sgdma_in_dev == NULL) { printf ("Error: Nie mozna otworzyc scatter-gather dma przesy³aj¹ce dane do zaszyfrowania do szyfratora 3DES\n"); return -1; } else alt_printf ("Otworzono scatter-gather dma sink-source device wysy³aj¹cy dane do szyfratora 3DES\n"); // Utworzenie odbiorczego deskryptora sgdma alt_avalon_sgdma_construct_stream_to_mem_desc( &tdesout_descriptor, &tdesout_descriptor_end, (alt_u32 *)blok_wynikow, 0, 0 ); // Uruchomienie wykonywania nie blokuj¹cego zapisu danych z SGDMA szyfratora 3des alt_avalon_sgdma_do_async_transfer( sgdma_out_dev, &tdesout_descriptor ); //Uruchomienie SGDMA dla deszyfratora Triple DES sgdma_out_decrypt_dev = alt_avalon_sgdma_open ("/dev/sgdma_3desdecrypt_out"); if (sgdma_out_decrypt_dev == NULL) { printf ("Error: nie mozna otworzyc scatter-gather dma odbieraj¹cego zdeszyfrowane dane 3DES\n"); return -1; } else alt_printf ("Otworzono scatter-gather dma source-sink odberaj¹cy odkodowane dane z deszyfratora 3DES\n"); sgdma_in_decrypt_dev = alt_avalon_sgdma_open ("/dev/sgdma_3desdecrypt_in"); if (sgdma_in_decrypt_dev == NULL) { printf ("Error: Nie mozna otworzyc scatter-gather dma przesy³aj¹ce dane do zdeszyfrowania do deszyfratora 3DES\n"); return -1; } else printf ("Otworzono scatter-gather dma sink-source device wysy³aj¹cy dane do deszyfratora 3DES\n"); // Utworzenie odbiorczego deskryptora sgdma alt_avalon_sgdma_construct_stream_to_mem_desc( &tdesdecryptout_descriptor, &tdesdecryptout_descriptor_end, (alt_u32 *)blok_wynikow_deszyfracja, 0, 0 ); // Uruchomienie wykonywania nie blokuj¹cego zapisu danych z SGDMA deszyfratora 3des alt_avalon_sgdma_do_async_transfer( sgdma_out_decrypt_dev, &tdesdecryptout_descriptor ); printf ("Cale SGDMA uruchomione\n"); // adresy bazowe komponentów Triple-speed Ethernet MegaCore volatile int * tse = (int *) ETH_TSE_BASE; volatile int * tse1 = (int *) ETH_TSE1_BASE; // Ustawienie adresu MAC 01-60-6E-11-02-0F na oba moduly TSE *(tse + 0x03) = 0x116E6001; *(tse + 0x04) = 0x00000F02; *(tse1 + 0x03) = 0x116E6001; *(tse1 + 0x04) = 0x00000F01; printf ("Ustalenie adresu MAC\n"); //Okreslenie adresow urzadzen PHY do ktorych dostep odbywac sie bedzie przez interfejs MDIO *(tse + 0x0F) = 0x10; *(tse + 0x10) = 0x11; //Okreslenie adresow urzadzen PHY do ktorych dostep odbywac sie bedzie przez interfejs MDIO *(tse1 + 0x0F) = 0x10; *(tse1 + 0x10) = 0x11; // Ustawienie crossoveru dla obu PHY *(tse + 0x94) = 0x4000; *(tse1 + 0x94) = 0x4000; //Uruchomienie crosoveru dla PHY *(tse + 0x90) = *(tse + 0x90) | 0x0060; // Wprowadzenie opoznienia zegara wejsciowego i wyjsciowego *(tse + 0x94) = *(tse + 0x94) | 0x0082; *(tse1 + 0x94) = *(tse1 + 0x94) | 0x0082; // Software reset obu chipow PHY *(tse + 0x80) = *(tse + 0x80) | 0x8000; while ( *(tse + 0x80) & 0x8000 ) ; *(tse1 + 0x02) = *(tse1 + 0x02) | 0x2000; while ( *(tse1 + 0x02) & 0x2000 ) ; //sprawdzenie czy reset sie zakonczyl (sw_reset=0) *(tse1 + 0xA0) = *(tse1 + 0xA0) | 0x8000; while ( *(tse1 + 0xA0) & 0x8000 ) ; printf("Udany reset obu modulow"); // Umozliwienie zapisu i odczytu ramek z blednie wyliczonym CRC *(tse + 2) = *(tse + 2) |0x040001F3; *(tse1 + 2) = *(tse1 + 2) |0x040001F3; // printf( "send> \n" ); text_length = 0; // wprowadzenie_kluczy(); //Wprowadzenie wartosci kluczy ktore mialy byc uzywane przy transmisji Ethernet weryfikacja_szyfrowania (); //tutaj ustawione zostaja wartosci kluczy szyfratora 3des //usleep(2500000); weryfikacja_deszyfrowania();//tutaj ustawione zostaja wartosci kluczy deszyfratora 3des // TODO odkomentowac jezeli chce sie przeprowadzic test wydajnosci szyfrowania na ukladzie FPGA test_wydajnosc (); test_wydajnosci_sram(); test_wydajnosci_3des_pot(); printf("adres udp_Data: %i", &blok_wynikow); if (ifdecipher_udp==2) { printf("udp_data"); } wprowadzenie_adresow_ip_do_3des(); while(1) { } return 0; }
int main (void) { FRESULT rc; /* Result code */ DIR dir; /* Directory object */ FILINFO fno; /* File information object */ unsigned long br, i; alt_u32* active_buff; printf("System started\r\n"); lcd_off(); for(i=0;i<5000000;i++){} alt_sgdma_dev *dma = alt_avalon_sgdma_open("/dev/sgdma"); printf("open dma returned %ld\n", (alt_u32)dma); printf("framebuffer 1 at %lx\n", (alt_u32)frameBufferA); printf("framebuffer 2 at %lx\n", (alt_u32)frameBufferB); active_buff = frameBufferA; //printf("framebuffer 1 at %lx\n", (alt_u32)active_buff); printf("Turning LCD on \r\n"); lcd_on(); printf("Starting DMA\r\n"); init_and_start_framebuffer(dma); IoInit(); Color col2; col2.color32 = 0x00ff0000; memset(frameBufferA, col2.color32, 522240/4); f_mount(0, &Fatfs); /* Register volume work area (never fails) */ for (;;) { printf("\nOpen root directory.\n"); rc = f_opendir(&dir, ""); if (rc) die(rc); printf("\nDirectory listing...\n"); for (;;) { rc = f_readdir(&dir, &fno); /* Read a directory item */ if (rc || !fno.fname[0]) break; /* Error or end of dir */ if (fno.fattrib & AM_DIR) printf(" <dir> %s\n", fno.fname); else { printf("%8lu %s\n", fno.fsize, fno.fname); //printf("\nOpen an existing file.\n"); rc = f_open(&Fil, fno.fname, FA_READ); if (rc) die(rc); if (active_buffer == 0) { active_buffer = 1; active_buff = frameBufferA; } else { active_buff = frameBufferB; active_buffer = 0; } for (;;) { rc = f_read(&Fil, (alt_u32*)active_buff, f_size(&Fil), &br); /* Read a chunk of file */ if (rc || !br) break; /* Error or end of file */ } if (rc) die(rc); rc = f_close(&Fil); if (rc) die(rc); } } if (rc) die(rc); } }
int main(int argc, char **argv) { char c; int uart_fd = open("/dev/uart", O_RDWR); if (uart_fd == NULL) { printf("Error opening uart\n"); return 1; } alt_sgdma_dev *transmit_dma = alt_avalon_sgdma_open("/dev/sgdma_0"); receive_dma = alt_avalon_sgdma_open("/dev/sgdma_1"); alt_sgdma_descriptor *transmit_descriptors[2], *transmit_descriptors_copy[2]; // alt_sgdma_descriptor *receive_descriptors[2], *receive_descriptors_copy[2]; alt_u32 *transmit_ptr, *receive_ptr; if (transmit_dma == NULL) { printf("Could not open transmit SG-DMA"); return 1; } if (receive_dma == NULL) { printf("Could not open the receive SG-DMA\n"); return 1; } alt_u32 return_code = descriptor_allocation(&transmit_descriptors[0], &transmit_descriptors_copy[0], &receive_descriptors[0], &receive_descriptors_copy[0], NUMBER_OF_BUFFERS); if (return_code == 1) { printf("Allocating the descriptor memory failed... exiting\n"); return 1; } return_code = descriptor_allocation(&transmit_descriptors[1], &transmit_descriptors_copy[1], &receive_descriptors[1], &receive_descriptors_copy[1], NUMBER_OF_BUFFERS); if (return_code == 1) { printf("Allocating the descriptor memory failed... exiting\n"); return 1; } printf("Transmit descriptor: 0x%08x\n", transmit_descriptors[0]); printf("Receive descriptor: 0x%08x\n", receive_descriptors[0]); alt_avalon_sgdma_register_callback(transmit_dma, &transmit_callback_function, (ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK | ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK), NULL); alt_avalon_sgdma_register_callback(receive_dma, &receive_callback_function, (ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK | ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK), NULL); printf("Starting up the SGDMA engines\n"); alt_u32* transmit_ptrs[2][NUMBER_OF_BUFFERS]; int i, j; for (j = 0; j < 2; j++) { for (i = 0; i < NUMBER_OF_BUFFERS; i++) { transmit_ptr = (alt_u32 *) malloc(MAXIMUM_BUFFER_LENGTH); // this descriptor will point at a buffer of length (temp_length) if (transmit_ptr == NULL) { printf("Allocating a transmit buffer region failed\n"); return 1; } transmit_ptrs[j][i] = transmit_ptr; } for (i = 0; i < NUMBER_OF_BUFFERS; i++) { alt_avalon_sgdma_construct_mem_to_stream_desc( &transmit_descriptors[j][i], // descriptor &transmit_descriptors[j][i + 1], // next descriptor transmit_ptrs[j][i], // read buffer location (alt_u16) MAXIMUM_BUFFER_LENGTH, // length of the buffer 0, // reads are not from a fixed location 0, // start of packet is enabled for the Avalon-ST interfaces 0, // end of packet is enabled for the Avalon-ST interfaces, 0); // there is only one channel } } // alt_u32* receive_ptrs[2][NUMBER_OF_BUFFERS]; for (j = 0; j < 2; j++) { for (i = 0; i < NUMBER_OF_BUFFERS; i++) { receive_ptr = (alt_u32 *) malloc(MAXIMUM_BUFFER_LENGTH); // this descriptor will point at a buffer of length (temp_length) if (receive_ptr == NULL) { printf("Allocating a receive buffer region failed\n"); return 1; } receive_ptrs[j][i] = receive_ptr; } for (i = 0; i < NUMBER_OF_BUFFERS; i++) { alt_avalon_sgdma_construct_stream_to_mem_desc( &receive_descriptors[j][i], // descriptor &receive_descriptors[j][i + 1], // next descriptor receive_ptrs[j][i], // read buffer location (alt_u16) MAXIMUM_BUFFER_LENGTH, // length of the buffer 0); // there is only one channel } } if (alt_avalon_sgdma_do_async_transfer(receive_dma, &receive_descriptors[dbufr][0]) != 0) { printf( "Writing the head of the receive descriptor list to the DMA failed\n"); return 1; } int buffer_counter = 0; int dbuft = 0; int char_count = 0; while (1) { int num_read = readall(uart_fd, transmit_ptrs[dbuft][buffer_counter], MAXIMUM_BUFFER_LENGTH); if (num_read > 0) { alt_avalon_sgdma_construct_mem_to_stream_desc( &transmit_descriptors[dbuft][buffer_counter], // descriptor &transmit_descriptors[dbuft][buffer_counter + 1], // next descriptor transmit_ptrs[dbuft][buffer_counter], // read buffer location (alt_u16) num_read, // length of the buffer 0, // reads are not from a fixed location 0, // start of packet is enabled for the Avalon-ST interfaces 0, // end of packet is enabled for the Avalon-ST interfaces, 0); // there is only one channel buffer_counter++; if (buffer_counter >= NUMBER_OF_BUFFERS) { buffer_counter = 0; dbuft++; if (dbuft > 1) { dbuft = 0; } if (tx_done) { if (alt_avalon_sgdma_do_async_transfer(transmit_dma, &transmit_descriptors[dbuft][0]) != 0) { printf( "Writing the head of the transmit descriptor list to the DMA failed\n"); return 1; } tx_done = 0; } } } /* if ((IORD(UART_BASE,2) & 0x80)) { c = IORD(UART_BASE, 0); *transmit_ptr++ = c; char_count++; if (char_count >= MAXIMUM_BUFFER_LENGTH) { char_count = 0; transmit_ptr = transmit_ptrs[dbuft][buffer_counter]; alt_avalon_sgdma_construct_mem_to_stream_desc( &transmit_descriptors[dbuft][buffer_counter], // descriptor &transmit_descriptors[dbuft][buffer_counter + 1], // next descriptor transmit_ptrs[dbuft][buffer_counter], // read buffer location (alt_u16) MAXIMUM_BUFFER_LENGTH, // length of the buffer 0, // reads are not from a fixed location 0, // start of packet is enabled for the Avalon-ST interfaces 0, // end of packet is enabled for the Avalon-ST interfaces, 0); // there is only one channel buffer_counter++; if (buffer_counter >= NUMBER_OF_BUFFERS) { buffer_counter = 0; dbuft++; if (dbuft > 1) { dbuft = 0; } if (tx_done) { if (alt_avalon_sgdma_do_async_transfer(transmit_dma, &transmit_descriptors[dbuft][0]) != 0) { printf( "Writing the head of the transmit descriptor list to the DMA failed\n"); return 1; } tx_done = 0; } } } } */ if (rx_done) { for (i = 0; i < NUMBER_OF_BUFFERS; i++) { write(uart_fd, receive_ptrs[dbufr][i], MAXIMUM_BUFFER_LENGTH); } rx_done = 0; } } return 0; }
/****************************************************************** * Function: alt_video_display_init * * Purpose: Initializes the display controller. Gets memory for the * frame buffer and descriptor buffers, intitalizes the * descriptors, sets the resolution of the frame buffers, * clears all the frame buffers, then finally opens * the SGDMA, registers the SGDMA callback function and * starts the SGDMA. * * Returns: *Note non-standard return code!*: * Pointer to the display controller structure, or NULL on failure. ******************************************************************/ alt_video_display* alt_video_display_init( char* sgdma_name, int width, int height, int color_depth, int buffer_location, int descriptor_location, int num_buffers) { alt_video_display* display; unsigned int bytes_per_pixel, bytes_per_frame, descriptors_per_frame, i; int result; // We'll need these values more than once, so let's pre-calculate them. bytes_per_pixel = color_depth >> 3; // same as /8 bytes_per_frame = (( width * height ) * bytes_per_pixel ); // Calculate the number of descriptors needed for each frame if( bytes_per_frame <= ALT_VIDEO_DISPLAY_BYTES_PER_DESC ) { descriptors_per_frame = 1; } else if(( bytes_per_frame % ALT_VIDEO_DISPLAY_BYTES_PER_DESC) == 0) { descriptors_per_frame = bytes_per_frame / ALT_VIDEO_DISPLAY_BYTES_PER_DESC; } else { descriptors_per_frame = ( bytes_per_frame / ALT_VIDEO_DISPLAY_BYTES_PER_DESC ) + 1; } // Check for too many frame buffers if( num_buffers > ALT_VIDEO_DISPLAY_MAX_BUFFERS ) { num_buffers = ALT_VIDEO_DISPLAY_MAX_BUFFERS; } // Allocate our display struct display = (alt_video_display*) malloc(sizeof(alt_video_display)); if(!display) { return NULL; } // Fill out the display structure display->width = width; display->height = height; display->color_depth = color_depth; display->num_frame_buffers = num_buffers; display->bytes_per_frame = bytes_per_frame; display->bytes_per_pixel = bytes_per_pixel; display->buffer_being_displayed = 0; display->buffer_being_written = (num_buffers > 1) ? 1:0; display->descriptors_per_frame = descriptors_per_frame; // Allocate our frame and descriptor buffers if(alt_video_display_allocate_buffers( display, bytes_per_frame, buffer_location, descriptor_location, num_buffers ) ) { return NULL; } // Now construct SGDMA descriptors for each frame buffer for( i = 0; i < num_buffers; i++ ) { alt_video_display_setup_frame_descriptors( display, // our display display->buffer_ptrs[i], // frame display->buffer_ptrs[i]->buffer, // frame location display->buffer_ptrs[i]->desc_base ); // descriptor memory } // Clear all frame buffers to black for( i = 0; i < num_buffers; i++ ) { memset( (void*)(display->buffer_ptrs[i]->buffer), ALT_VIDEO_DISPLAY_BLACK_8, display->bytes_per_frame ); } // Open the SGDMA display->sgdma = alt_avalon_sgdma_open(sgdma_name); if(!display->sgdma) { return NULL; } /* Enable SGDMA "parking" mode */ IOWR_ALTERA_AVALON_SGDMA_CONTROL(LCD_SGDMA_BASE, ALTERA_AVALON_SGDMA_CONTROL_PARK_MSK); /* Now start the SGDMA */ result = alt_avalon_sgdma_do_async_transfer( display->sgdma, display->buffer_ptrs[display->buffer_being_displayed]->desc_base); if(result) { return NULL; } return ( display ); }
int main (int argc, char* argv[], char* envp[]) { //dane=0; /** * Inicjalizacja danych do szyfrowania */ printf("Rozpoczecie dzialania programu\n"); //init_3des ( key11, key12, key21, key22, key31, key32); //Otworzenie transmitujacego SGDMA dla TSE0 sgdma_tx_dev = alt_avalon_sgdma_open ("/dev/sgdma_tx"); if (sgdma_tx_dev == NULL) { alt_printf ("Error: nie mozna otworzyc scatter-gather dma transmit device dla TSE0\n"); return -1; } else alt_printf ("Otworzono scatter-gather dma transmit device dla TSE0\n"); //Otworzenie odbierajacego SGDMA dla TSE0 sgdma_rx_dev = alt_avalon_sgdma_open ("/dev/sgdma_rx"); if (sgdma_rx_dev == NULL) { alt_printf ("Error: nie mozna otworzyc scatter-gather dma receive device dla TSE0\n"); return -1; } else alt_printf ("Otworzno scatter-gather dma receive devicedla TSE0\n"); printf ("System uruchomiony\n"); alt_avalon_sgdma_register_callback( sgdma_rx_dev, (alt_avalon_sgdma_callback) rx_ethernet_isr, 0x00000014, NULL ); // Utworzenie odbiorczego deskryptora sgdma alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor, &rx_descriptor_end, (alt_u32 *)rx_frame, 0, 0 ); alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev, &rx_descriptor ); // Uruchomienie drugiego SGDMA // // //Otworzenie transmitujacego SGDMA dla TSE1 alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev1, &rx_descriptor1 ); sgdma_tx_dev1 = alt_avalon_sgdma_open ("/dev/sgdma_tx1"); if (sgdma_tx_dev1 == NULL) { alt_printf ("Error: nie mozna otworzyc scatter-gather dma transmit device dla TSE1\n"); return -1; } else alt_printf ("Otworzono scatter-gather dma transmit device dla TSE1\n"); //Otworzenie odbierajacego SGDMA dla TSE1 sgdma_rx_dev1 = alt_avalon_sgdma_open ("/dev/sgdma_rx1"); if (sgdma_rx_dev1 == NULL) { alt_printf ("Error: nie mozna otworzyc scatter-gather dma receive device dla TSE1\n"); return -1; } else alt_printf ("Otworzno scatter-gather dma receive devicedla TSE1\n"); printf ("System uruchomiony\n"); alt_avalon_sgdma_register_callback( sgdma_rx_dev1, (alt_avalon_sgdma_callback) rx_ethernet_isr1, 0x00000014, NULL ); //// Utworzenie odbiorczego deskryoptora sgdma alt_avalon_sgdma_construct_stream_to_mem_desc( &rx_descriptor1, &rx_descriptor_end1,(alt_u32 *) rx_frame1, 0, 0 ); // Set up non-blocking transfer of sgdma receive descriptor alt_avalon_sgdma_do_async_transfer( sgdma_rx_dev1, &rx_descriptor1 ); //Uruchomienie trzeciego SGDMA //Otworzenie SGDMA memory to memory dla obslugi wymiany pamieci pomiedzy SRAM a glowna pamiecia /*sgdma_read_3des = alt_avalon_sgdma_open ("/dev/sgdma_0"); if (sgdma_read_3des == NULL) { alt_printf ("Error: Nie mozna otworzyc scatter-gather dma memory-memory device dla obslugi pamieci SRAM\n"); return -1; } else alt_printf ("Otworzono scatter-gather dma memory-memory device dla obslugi pamieci SRAM\n"); */ printf ("Cale SGDMA uruchomione\n"); /* * weryfikacja_szyfrowania (); weryfikacja_deszyfrowania(); przygotowanie_danych(); test_wydajnosc (); test_wydajnosci_sram(); */ // adresy bazoweTriple-speed Ethernet MegaCore volatile int * tse = (int *) ETH_TSE_BASE; //volatile int * tse = (int *) 0x103400; volatile int * tse1 = (int *) ETH_TSE1_BASE; //volatile int * tse1 = (int *) 0x103000; // Ustawienie adresu MAC 01-60-6E-11-02-0F na oba moduly TSE *(tse + 0x03) = 0x116E6001; *(tse + 0x04) = 0x00000F02; *(tse1 + 0x03) = 0x116E6001; *(tse1 + 0x04) = 0x00000F01; // alt_tse_mac_set_common_speed(ETH_TSE_BASE,2); printf ("Ustalenie adresu MAC\n"); // Okreslenie adresow urzadzen PHY do ktorych dostep odbywac sie bedzie przez interfejs MDIO *(tse + 0x0F) = 0x10; *(tse + 0x10) = 0x11; // Okreslenie adresow urzadzen PHY do ktorych dostep odbywac sie bedzie przez interfejs MDIO /// *(tse1 + 0x0F) = 0x10; /// *(tse1 + 0x10) = 0x11; // Write to register 20 of the PHY chip for Ethernet port 0 to set up line loopback //*(tse + 0x94 ) = 0x4000; // Ustawienie crossoveru dla obu PHY // *(tse + 0xA0) = *(tse + 0xA0) | 0x0060; /// *(tse1 + 0xB0) = *(tse1 + 0xB0) | 0x0060; *(tse + 0x94) = 0x4000; //Uruchomienie crosoveru dla PHY *(tse + 0x90) = *(tse + 0x90) | 0x0060; // *(tse1 + 0xB0) = *(tse1 + 0xB0) | 0x0060; // Wprowadzenie opoznienia zegara wejsciowego i wyjsciowego /// *(tse1 + 0xB4) = *(tse1 + 0xB4) | 0x0082; *(tse + 0x94) = *(tse + 0x94) | 0x0082; // *(tse + 2) = *(tse + 2) | 0x02000043; // Software reset obu chipow PHY *(tse + 0x80) = *(tse + 0x80) | 0x8000; while ( *(tse + 0x80) & 0x8000 ) ; // *(tse + 0x02) = *(tse + 0x02) | 0x2000; // while ( *(tse + 0x02) & 0x2000 ) ; //sprawdzenie czy reset sie zakonczyl (sw_reset=0) /// *(tse1 + 0xA0) = *(tse1 + 0xA0) | 0x8000; /// while ( *(tse1 + 0xA0) & 0x8000 ) ; // Umozliwienie zapisu i odczytu oraz przesylania ramek z blednie wyliczonym CRC printf("Udany reset obu modulow"); /// *(tse1 + 2) = *(tse1 + 2) | 0x02000043; // *(tse + 2 ) = *(tse + 2) | 0x0000004B; *(tse + 2) = *(tse + 2) |0x040001F3; alt_printf( "send> " ); text_length = 0; // wprowadzenie_kluczy(); //Wprowadzenie wartosci kluczy ktore mialy byc uzywane przy transmisji Ethernet while (1) { char new_char; // tx_frame[16] = '\0'; while ( (new_char = alt_getchar()) != '\n' ) { if (new_char == 0x08 && text_length > 0) { alt_printf( "%c", new_char ); text_length--; // Maintain the terminal character after the text tx_frame[16 + text_length] = '\0'; } else if (text_length < 45) { //alt_printf( "%c", new_char ); unsigned int bajt1, tmp; unsigned char bajt2=0x1024000; unsigned char szyfr_new_char; //szyfr_new_char=IORD(SZYFRXOR_0_BASE,0); // Add the new character to the output text tx_frame[16 + text_length] = new_char; text_length++; //printf ("wewnatrz tu tu"); tx_frame[16 + text_length] = '\0'; //alt_printf( "%c", szyfr_new_char ); // printf( "x%2X", new_char); // printf( "x%2X", szyfr_new_char); // printf( "x%2X", bajt2); // printf ("%s", rx_frame); //printf( "x%2X", bajt2); } } // *phy1 = *(tse + 0x2C); //printf("Liczba odebranych pakietow: %X",phy1); alt_printf( "\nsend> " ); text_length = 0; //usleep(2000000); //alt_avalon_sgdma_construct_mem_to_stream_desc( &tx_descriptor, &tx_descriptor_end, rx_frame, 90, 0, 1, 1, 0 ); //alt_avalon_sgdma_do_async_transfer( sgdma_tx_dev, &tx_descriptor ); //while (alt_avalon_sgdma_check_descriptor_status(&tx_descriptor) != 0) // ; } while(1) { //printf("petla while odbieranie i wysylanie"); // while (alt_avalon_sgdma_check_descriptor_status(&rx_descriptor) != 0); // printf("petla while odbieranie i wysylanie"); } return 0; }