static void aucodec_digitalio_on_1(void)
{
/* aucodec_digitalio_on */
#if (CHIP_REV == A3)||(CHIP_REV == A5)||(CHIP_REV == A6)|| \
(CHIP_REV == A5S)||(CHIP_REV == I1)||(CHIP_REV == S2)
unsigned long flags;
ambarella_gpio_raw_lock(1, &flags);
amba_clrbitsl(GPIO1_AFSEL_REG, 0x80000000);
ambarella_gpio_raw_unlock(1, &flags);
/* GPIO77~GPIO78 and GPIO81~GPIO83 program as hardware mode */
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, 0x000e6000);
ambarella_gpio_raw_unlock(2, &flags);
#elif (CHIP_REV == S2)
unsigned long flags;
ambarella_gpio_raw_lock(3, &flags);
amba_clrbitsl(GPIO3_AFSEL_REG, 0x0000000c);
ambarella_gpio_raw_unlock(3, &flags);
/* GPIO82~GPIO83 program as hardware mode */
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, 0x000c0000);
ambarella_gpio_raw_unlock(2, &flags);
#else
pr_err("aucodec_digitalio_on: Unknown Chip Architecture\n");
#endif
}
int __init ambarella_init_fio(void)
{
#if defined(CONFIG_AMBARELLA_FIO_FORCE_SDIO_GPIO)
unsigned long flags;
//SMIO_38 ~ SMIO_43
ambarella_gpio_raw_lock(2, &flags);
amba_clrbitsl(GPIO2_AFSEL_REG, 0x000007e0);
amba_clrbitsl(GPIO2_DIR_REG, 0x00000780);
amba_setbitsl(GPIO2_DIR_REG, 0x00000060);
amba_writel(GPIO2_MASK_REG, 0x00000060);
amba_writel(GPIO2_DATA_REG, 0x00000040);
ambarella_gpio_raw_unlock(2, &flags);
#endif
return 0;
}
static void aucodec_digitalio_on_0(void)
{
/* aucodec_digitalio_on */
#if (CHIP_REV == A2S) || (CHIP_REV == A2M)
unsigned long flags;
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, (0xf << 18) | (0xf << 13));
ambarella_gpio_raw_unlock(2, &flags);
#elif (CHIP_REV == A2)
unsigned long flags;
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, (0x3 << 15) | (0x3 << 20));
ambarella_gpio_raw_unlock(2, &flags);
#elif (CHIP_REV == A3)||(CHIP_REV == A5)||(CHIP_REV == A6)|| \
(CHIP_REV == A5S)||(CHIP_REV == I1)
unsigned long flags;
ambarella_gpio_raw_lock(1, &flags);
amba_clrbitsl(GPIO1_AFSEL_REG, 0x80000000);
ambarella_gpio_raw_unlock(1, &flags);
/* GPIO77~GPIO81 program as hardware mode */
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, 0x0003e000);
ambarella_gpio_raw_unlock(2, &flags);
#elif (CHIP_REV == S2)
unsigned long flags;
ambarella_gpio_raw_lock(3, &flags);
amba_clrbitsl(GPIO3_AFSEL_REG, 0x00000030);
ambarella_gpio_raw_unlock(3, &flags);
/* GPIO77~GPIO81 program as hardware mode */
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, 0x0003e000);
ambarella_gpio_raw_unlock(2, &flags);
#else
pr_err("aucodec_digitalio_on: Unknown Chip Architecture\n");
#endif
}
int __init ambarella_init_fio(void)
{
fio_amb_exit_random_mode();
enable_fio_dma();
amba_writel(FLASH_INT_REG, 0x0);
amba_writel(XD_INT_REG, 0x0);
amba_writel(CF_STA_REG, CF_STA_CW | CF_STA_DW);
//#if defined(CONFIG_AMBARELLA_FIO_FORCE_SDIO_GPIO)
unsigned long flags;
//SMIO_38 ~ SMIO_43
ambarella_gpio_raw_lock(2, &flags);
amba_clrbitsl(GPIO2_AFSEL_REG, 0x000007e0);
amba_clrbitsl(GPIO2_DIR_REG, 0x00000780);
amba_setbitsl(GPIO2_DIR_REG, 0x00000060);
amba_writel(GPIO2_MASK_REG, 0x00000060);
amba_writel(GPIO2_DATA_REG, 0x00000040);
ambarella_gpio_raw_unlock(2, &flags);
//#endif
return 0;
}
/* ==========================================================================*/
void __fio_select_lock(int module)
{
u32 fio_ctr;
u32 fio_dmactr;
#if (SD_HAS_INTERNAL_MUXER == 1)
unsigned long flags;
#endif
fio_ctr = amba_readl(FIO_CTR_REG);
fio_dmactr = amba_readl(FIO_DMACTR_REG);
switch (module) {
case SELECT_FIO_FL:
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_FL;
break;
case SELECT_FIO_XD:
fio_ctr |= FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_XD;
break;
case SELECT_FIO_CF:
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_CF;
#if (FIO_SUPPORT_AHB_CLK_ENA == 1)
fio_amb_sd2_disable();
fio_amb_cf_enable();
#endif
break;
case SELECT_FIO_SD:
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_SD;
break;
case SELECT_FIO_SDIO:
fio_ctr |= FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_SD;
break;
case SELECT_FIO_SD2:
#if (FIO_SUPPORT_AHB_CLK_ENA == 1)
fio_amb_cf_disable();
fio_amb_sd2_enable();
#endif
#if (SD_HOST1_HOST2_HAS_MUX == 1)
fio_ctr &= ~FIO_CTR_XD;
fio_dmactr = (fio_dmactr & 0xcfffffff) | FIO_DMACTR_SD;
#endif
break;
default:
break;
}
#if (SD_HAS_INTERNAL_MUXER == 1)
spin_lock_irqsave(&fio_sd0_int_lock, flags);
amba_clrbitsl(SD_NISEN_REG, SD_NISEN_CARD);
spin_unlock_irqrestore(&fio_sd0_int_lock, flags);
#if defined(CONFIG_AMBARELLA_FIO_FORCE_SDIO_GPIO)
if (module != SELECT_FIO_SDIO) {
ambarella_gpio_raw_lock(2, &flags);
amba_clrbitsl(GPIO2_AFSEL_REG, 0x000007e0);
ambarella_gpio_raw_unlock(2, &flags);
}
#endif
#endif
amba_writel(FIO_CTR_REG, fio_ctr);
amba_writel(FIO_DMACTR_REG, fio_dmactr);
#if (SD_HAS_INTERNAL_MUXER == 1)
if (module == SELECT_FIO_SD) {
spin_lock_irqsave(&fio_sd0_int_lock, flags);
amba_writel(SD_NISEN_REG, fio_sd_int);
amba_writel(SD_NIXEN_REG, fio_sd_int);
spin_unlock_irqrestore(&fio_sd0_int_lock, flags);
} else
if (module == SELECT_FIO_SDIO) {
#if defined(CONFIG_AMBARELLA_FIO_FORCE_SDIO_GPIO)
ambarella_gpio_raw_lock(2, &flags);
amba_setbitsl(GPIO2_AFSEL_REG, 0x000007e0);
ambarella_gpio_raw_unlock(2, &flags);
#endif
spin_lock_irqsave(&fio_sd0_int_lock, flags);
amba_writel(SD_NISEN_REG, fio_sdio_int);
amba_writel(SD_NIXEN_REG, fio_sdio_int);
spin_unlock_irqrestore(&fio_sd0_int_lock, flags);
}
#endif
}
