static int amd_fam14h_init(cstate_t *state, unsigned int cpu) { int enable_bit, pci_offset, ret; uint32_t val; ret = amd_fam14h_get_pci_info(state, &pci_offset, &enable_bit, cpu); if (ret) return ret; if (state->id == NBP1) { val = pci_read_long(amd_fam14h_pci_dev, pci_offset); val |= 1 << enable_bit; val = pci_write_long(amd_fam14h_pci_dev, pci_offset, val); return ret; } val = pci_read_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG); dprint("Init %s: read at offset: 0x%x val: %u\n", state->name, PCI_MONITOR_ENABLE_REG, (unsigned int) val); val |= 1 << enable_bit; pci_write_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG, val); dprint("Init %s: offset: 0x%x enable_bit: %d - val: %u (%u)\n", state->name, PCI_MONITOR_ENABLE_REG, enable_bit, (unsigned int) val, cpu); pci_write_long(amd_fam14h_pci_dev, pci_offset, 0); previous_count[state->id][cpu] = 0; return 0; }
static int amd_fam14h_disable(cstate_t *state, unsigned int cpu) { int enable_bit, pci_offset, ret; uint32_t val; ret = amd_fam14h_get_pci_info(state, &pci_offset, &enable_bit, cpu); if (ret) return ret; val = pci_read_long(amd_fam14h_pci_dev, pci_offset); dprint("%s: offset: 0x%x %u\n", state->name, pci_offset, val); if (state->id == NBP1) { nbp1_entered = (val & (1 << PCI_NBP1_ACTIVE_BIT)) | (val & (1 << PCI_NBP1_ENTERED_BIT)); dprint("NBP1 was %sentered - 0x%x - enable_bit: " "%d - pci_offset: 0x%x\n", nbp1_entered ? "" : "not ", val, enable_bit, pci_offset); return ret; } current_count[state->id][cpu] = val; dprint("%s: Current - %llu (%u)\n", state->name, current_count[state->id][cpu], cpu); dprint("%s: Previous - %llu (%u)\n", state->name, previous_count[state->id][cpu], cpu); val = pci_read_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG); val &= ~(1 << enable_bit); pci_write_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG, val); return 0; }
static int amd_fam14h_init(cstate_t *state, unsigned int cpu) { int enable_bit, pci_offset, ret; uint32_t val; ret = amd_fam14h_get_pci_info(state, &pci_offset, &enable_bit, cpu); if (ret) return ret; /* NBP1 needs extra treating -> write 1 to D18F6x98 bit 1 for init */ if (state->id == NBP1) { val = pci_read_long(amd_fam14h_pci_dev, pci_offset); val |= 1 << enable_bit; val = pci_write_long(amd_fam14h_pci_dev, pci_offset, val); return ret; } /* Enable monitor */ val = pci_read_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG); dprint("Init %s: read at offset: 0x%x val: %u\n", state->name, PCI_MONITOR_ENABLE_REG, (unsigned int) val); val |= 1 << enable_bit; pci_write_long(amd_fam14h_pci_dev, PCI_MONITOR_ENABLE_REG, val); dprint("Init %s: offset: 0x%x enable_bit: %d - val: %u (%u)\n", state->name, PCI_MONITOR_ENABLE_REG, enable_bit, (unsigned int) val, cpu); /* Set counter to zero */ pci_write_long(amd_fam14h_pci_dev, pci_offset, 0); previous_count[state->id][cpu] = 0; return 0; }