/* on DCE5, make sure the voltage is high enough to support the * required disp clk. */ void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev, u32 dispclk) { u8 frev, crev; int index; union set_pixel_clock args; memset(&args, 0, sizeof(args)); index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) return; switch (frev) { case 1: switch (crev) { case 5: /* if the default dcpll clock is specified, * SetPixelClock provides the dividers */ args.v5.ucCRTC = ATOM_CRTC_INVALID; args.v5.usPixelClock = cpu_to_le16(dispclk); args.v5.ucPpll = ATOM_DCPLL; break; case 6: /* if the default dcpll clock is specified, * SetPixelClock provides the dividers */ args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); if (adev->asic_type == CHIP_TAHITI || adev->asic_type == CHIP_PITCAIRN || adev->asic_type == CHIP_VERDE || adev->asic_type == CHIP_OLAND) args.v6.ucPpll = ATOM_PPLL0; else args.v6.ucPpll = ATOM_EXT_PLL1; break; default: DRM_ERROR("Unknown table version %d %d\n", frev, crev); return; } break; default: DRM_ERROR("Unknown table version %d %d\n", frev, crev); return; } amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); }
u32 amdgpu_atombios_crtc_set_dce_clock(struct amdgpu_device *adev, u32 freq, u8 clk_type, u8 clk_src) { u8 frev, crev; int index; union set_dce_clock args; u32 ret_freq = 0; memset(&args, 0, sizeof(args)); index = GetIndexIntoMasterTable(COMMAND, SetDCEClock); if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) return 0; switch (frev) { case 2: switch (crev) { case 1: args.v2_1.asParam.ulDCEClkFreq = cpu_to_le32(freq); /* 10kHz units */ args.v2_1.asParam.ucDCEClkType = clk_type; args.v2_1.asParam.ucDCEClkSrc = clk_src; amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); ret_freq = le32_to_cpu(args.v2_1.asParam.ulDCEClkFreq) * 10; break; default: DRM_ERROR("Unknown table version %d %d\n", frev, crev); return 0; } break; default: DRM_ERROR("Unknown table version %d %d\n", frev, crev); return 0; } return ret_freq; }
void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct amdgpu_atom_ss *ss) { struct drm_device *dev = crtc->dev; struct amdgpu_device *adev = dev->dev_private; u8 frev, crev; int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); union set_pixel_clock args; memset(&args, 0, sizeof(args)); if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) return; switch (frev) { case 1: switch (crev) { case 1: if (clock == ATOM_DISABLE) return; args.v1.usPixelClock = cpu_to_le16(clock / 10); args.v1.usRefDiv = cpu_to_le16(ref_div); args.v1.usFbDiv = cpu_to_le16(fb_div); args.v1.ucFracFbDiv = frac_fb_div; args.v1.ucPostDiv = post_div; args.v1.ucPpll = pll_id; args.v1.ucCRTC = crtc_id; args.v1.ucRefDivSrc = 1; break; case 2: args.v2.usPixelClock = cpu_to_le16(clock / 10); args.v2.usRefDiv = cpu_to_le16(ref_div); args.v2.usFbDiv = cpu_to_le16(fb_div); args.v2.ucFracFbDiv = frac_fb_div; args.v2.ucPostDiv = post_div; args.v2.ucPpll = pll_id; args.v2.ucCRTC = crtc_id; args.v2.ucRefDivSrc = 1; break; case 3: args.v3.usPixelClock = cpu_to_le16(clock / 10); args.v3.usRefDiv = cpu_to_le16(ref_div); args.v3.usFbDiv = cpu_to_le16(fb_div); args.v3.ucFracFbDiv = frac_fb_div; args.v3.ucPostDiv = post_div; args.v3.ucPpll = pll_id; if (crtc_id == ATOM_CRTC2) args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; else args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; args.v3.ucTransmitterId = encoder_id; args.v3.ucEncoderMode = encoder_mode; break; case 5: args.v5.ucCRTC = crtc_id; args.v5.usPixelClock = cpu_to_le16(clock / 10); args.v5.ucRefDiv = ref_div; args.v5.usFbDiv = cpu_to_le16(fb_div); args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); args.v5.ucPostDiv = post_div; args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) && (pll_id < ATOM_EXT_PLL1)) args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { switch (bpc) { case 8: default: args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; break; case 10: /* yes this is correct, the atom define is wrong */ args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP; break; case 12: /* yes this is correct, the atom define is wrong */ args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; break; } } args.v5.ucTransmitterID = encoder_id; args.v5.ucEncoderMode = encoder_mode; args.v5.ucPpll = pll_id; break; case 6: args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); args.v6.ucRefDiv = ref_div; args.v6.usFbDiv = cpu_to_le16(fb_div); args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); args.v6.ucPostDiv = post_div; args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) && (pll_id < ATOM_EXT_PLL1) && !is_pixel_clock_source_from_pll(encoder_mode, pll_id)) args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { switch (bpc) { case 8: default: args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; break; case 10: args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; break; case 12: args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; break; case 16: args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; break; } } args.v6.ucTransmitterID = encoder_id; args.v6.ucEncoderMode = encoder_mode; args.v6.ucPpll = pll_id; break; default: DRM_ERROR("Unknown table version %d %d\n", frev, crev); return; } break; default: DRM_ERROR("Unknown table version %d %d\n", frev, crev); return; } amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); }
static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct drm_device *dev = crtc->dev; struct amdgpu_device *adev = dev->dev_private; struct drm_encoder *encoder = amdgpu_crtc->encoder; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); u32 adjusted_clock = mode->clock; int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(encoder); u32 dp_clock = mode->clock; u32 clock = mode->clock; int bpc = amdgpu_crtc->bpc; bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock); union adjust_pixel_clock args; u8 frev, crev; int index; amdgpu_crtc->pll_flags = AMDGPU_PLL_USE_FRAC_FB_DIV; if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { if (connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv; dp_clock = dig_connector->dp_clock; } } /* use recommended ref_div for ss */ if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { if (amdgpu_crtc->ss_enabled) { if (amdgpu_crtc->ss.refdiv) { amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV; amdgpu_crtc->pll_reference_div = amdgpu_crtc->ss.refdiv; amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV; } } } /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ if (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) adjusted_clock = mode->clock * 2; if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) amdgpu_crtc->pll_flags |= AMDGPU_PLL_PREFER_CLOSEST_LOWER; if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) amdgpu_crtc->pll_flags |= AMDGPU_PLL_IS_LCD; /* adjust pll for deep color modes */ if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { switch (bpc) { case 8: default: break; case 10: clock = (clock * 5) / 4; break; case 12: clock = (clock * 3) / 2; break; case 16: clock = clock * 2; break; } } /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock * accordingly based on the encoder/transmitter to work around * special hw requirements. */ index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) return adjusted_clock; memset(&args, 0, sizeof(args)); switch (frev) { case 1: switch (crev) { case 1: case 2: args.v1.usPixelClock = cpu_to_le16(clock / 10); args.v1.ucTransmitterID = amdgpu_encoder->encoder_id; args.v1.ucEncodeMode = encoder_mode; if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage) args.v1.ucConfig |= ADJUST_DISPLAY_CONFIG_SS_ENABLE; amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; break; case 3: args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); args.v3.sInput.ucTransmitterID = amdgpu_encoder->encoder_id; args.v3.sInput.ucEncodeMode = encoder_mode; args.v3.sInput.ucDispPllConfig = 0; if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage) args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_SS_ENABLE; if (ENCODER_MODE_IS_DP(encoder_mode)) { args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_COHERENT_MODE; /* 16200 or 27000 */ args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); } else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; if (dig->coherent_mode) args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_COHERENT_MODE; if (is_duallink) args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_DUAL_LINK; } if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) args.v3.sInput.ucExtTransmitterID = amdgpu_encoder_get_dp_bridge_encoder_id(encoder); else args.v3.sInput.ucExtTransmitterID = 0; amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; if (args.v3.sOutput.ucRefDiv) { amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV; amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV; amdgpu_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; } if (args.v3.sOutput.ucPostDiv) { amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV; amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_POST_DIV; amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; } break; default: DRM_ERROR("Unknown table version %d %d\n", frev, crev); return adjusted_clock; } break; default: DRM_ERROR("Unknown table version %d %d\n", frev, crev); return adjusted_clock; } return adjusted_clock; }