static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { bool int_handled = true; DRM_DEBUG("IH: UVD TRAP\n"); switch (entry->src_id) { case 124: amdgpu_fence_process(&adev->uvd.inst->ring); break; case 119: if (likely(uvd_v6_0_enc_support(adev))) amdgpu_fence_process(&adev->uvd.inst->ring_enc[0]); else int_handled = false; break; case 120: if (likely(uvd_v6_0_enc_support(adev))) amdgpu_fence_process(&adev->uvd.inst->ring_enc[1]); else int_handled = false; break; } if (false == int_handled) DRM_ERROR("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); return 0; }
static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) { struct drm_info_node *node = (struct drm_info_node *)m->private; struct drm_device *dev = node->minor->dev; struct amdgpu_device *adev = dev->dev_private; int i; for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = adev->rings[i]; if (!ring || !ring->fence_drv.initialized) continue; amdgpu_fence_process(ring); seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); seq_printf(m, "Last signaled fence 0x%08x\n", atomic_read(&ring->fence_drv.last_seq)); seq_printf(m, "Last emitted 0x%08x\n", ring->fence_drv.sync_seq); if (ring->funcs->type != AMDGPU_RING_TYPE_GFX) continue; /* set in CP_VMID_PREEMPT and preemption occurred */ seq_printf(m, "Last preempted 0x%08x\n", le32_to_cpu(*(ring->fence_drv.cpu_addr + 2))); /* set in CP_VMID_RESET and reset occurred */ seq_printf(m, "Last reset 0x%08x\n", le32_to_cpu(*(ring->fence_drv.cpu_addr + 4))); /* Both preemption and reset occurred */ seq_printf(m, "Last both 0x%08x\n", le32_to_cpu(*(ring->fence_drv.cpu_addr + 6))); } return 0; }
/** * amdgpu_fence_fallback - fallback for hardware interrupts * * @work: delayed work item * * Checks for fence activity. */ static void amdgpu_fence_fallback(struct timer_list *t) { struct amdgpu_ring *ring = from_timer(ring, t, fence_drv.fallback_timer); amdgpu_fence_process(ring); }
static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { DRM_DEBUG("IH: UVD TRAP\n"); amdgpu_fence_process(&adev->uvd.ring); return 0; }
static int si_dma_process_trap_irq_1(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { amdgpu_fence_process(&adev->sdma.instance[1].ring); return 0; }
static int vce_v2_0_process_interrupt(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { DRM_DEBUG("IH: VCE\n"); switch (entry->src_data) { case 0: amdgpu_fence_process(&adev->vce.ring[0]); break; case 1: amdgpu_fence_process(&adev->vce.ring[1]); break; default: DRM_ERROR("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); break; } return 0; }
static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { u8 instance_id, queue_id; instance_id = (entry->ring_id & 0x3) >> 0; queue_id = (entry->ring_id & 0xc) >> 2; DRM_DEBUG("IH: SDMA trap\n"); switch (instance_id) { case 0: switch (queue_id) { case 0: amdgpu_fence_process(&adev->sdma.instance[0].ring); break; case 1: /* XXX compute */ break; case 2: /* XXX compute */ break; } break; case 1: switch (queue_id) { case 0: amdgpu_fence_process(&adev->sdma.instance[1].ring); break; case 1: /* XXX compute */ break; case 2: /* XXX compute */ break; } break; } return 0; }
/** * amdgpu_fence_count_emitted - get the count of emitted fences * * @ring: ring the fence is associated with * * Get the number of fences emitted on the requested ring (all asics). * Returns the number of emitted fences on the ring. Used by the * dynpm code to ring track activity. */ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring) { uint64_t emitted; /* We are not protected by ring lock when reading the last sequence * but it's ok to report slightly wrong fence count here. */ amdgpu_fence_process(ring); emitted = 0x100000000ull; emitted -= atomic_read(&ring->fence_drv.last_seq); emitted += ACCESS_ONCE(ring->fence_drv.sync_seq); return lower_32_bits(emitted); }
static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data) { struct drm_info_node *node = (struct drm_info_node *)m->private; struct drm_device *dev = node->minor->dev; struct amdgpu_device *adev = dev->dev_private; int i; for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = adev->rings[i]; if (!ring || !ring->fence_drv.initialized) continue; amdgpu_fence_process(ring); seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name); seq_printf(m, "Last signaled fence 0x%08x\n", atomic_read(&ring->fence_drv.last_seq)); seq_printf(m, "Last emitted 0x%08x\n", ring->fence_drv.sync_seq); } return 0; }
/** * amdgpu_fence_fallback - fallback for hardware interrupts * * @work: delayed work item * * Checks for fence activity. */ static void amdgpu_fence_fallback(unsigned long arg) { struct amdgpu_ring *ring = (void *)arg; amdgpu_fence_process(ring); }