/*as use the spin_lock,
*1--there is no sleep,
*2--it is better to shorter the time,
*/
int amcsi_isr(struct tvin_frontend_s *fe, unsigned int hcnt)
{
struct amcsi_dev_s *devp = container_of(fe, amcsi_dev_t, frontend);
unsigned data1 = 0;
unsigned data2 = 0;
am_csi2_frame_t frame;
frame.w = aml_get_reg32_bits( P_CSI2_PIC_SIZE_STAT, 0, 16);
frame.h = aml_get_reg32_bits( P_CSI2_PIC_SIZE_STAT, 16,16);
frame.err = aml_read_reg32( P_CSI2_ERR_STAT0 );
data1 = aml_read_reg32( P_CSI2_DATA_TYPE_IN_MEM);
data2 = aml_read_reg32( P_CSI2_GEN_STAT0);
if(frame.err){
mipi_error("%s,error---pixel cnt:%d, line cnt:%d. error state:0x%x.mem type:0x%x, status:0x%x\n",
__func__, frame.w, frame.h, frame.err, data1, data2);
devp->overflow_cnt ++;
aml_write_reg32( P_CSI2_ERR_STAT0, 0);
}
if( devp->overflow_cnt > 4){
DPRINT("should reset mipi\n");
devp->overflow_cnt = 0;
return 0;
}
devp->reset = 0;
return 0;
}
int gpio_amlogic_get(struct gpio_chip *chip,unsigned offset)
{
unsigned int reg,bit;
gpio_print("==%s==%d\n",__FUNCTION__,__LINE__);
reg=GPIO_REG(amlogic_pins[offset].input_value_reg_bit);
bit=GPIO_BIT(amlogic_pins[offset].input_value_reg_bit);
return aml_get_reg32_bits(p_gpio_input_addr[reg],bit,1);
}
void clk_switch(int flag)
{
int i;
if (flag) {
for (i = CLK_COUNT - 1; i >= 0; i--) {
if (clk_flag[i]) {
if ((clks[i] == P_HHI_VID_CLK_CNTL)||(clks[i] == P_HHI_VIID_CLK_CNTL)) {
aml_set_reg32_bits(clks[i],clk_flag[i],19,2);
} else if (clks[i] == P_HHI_MPEG_CLK_CNTL) {
if(uart_rate_backup == 0){
struct clk* sys_clk = clk_get_sys("clk81", NULL);
sys_clk->rate = 0;
uart_rate_backup = clk_get_rate(sys_clk);
}
wait_uart_empty();
aml_set_reg32_mask(clks[i],(1<<7));//gate on pll
udelay(10);
aml_set_reg32_mask(clks[i],(1<<8));//switch to pll
udelay(10);
aml_clr_reg32_mask(P_UART0_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_UART0_REG5, ((uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_UART0_REG5, 1, 23, 1);
aml_clr_reg32_mask(P_UART1_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_UART1_REG5, ((uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_UART1_REG5, 1, 23, 1);
aml_clr_reg32_mask(P_AO_UART2_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_AO_UART2_REG5, ((uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_AO_UART2_REG5, 1, 23, 1);
aml_clr_reg32_mask(P_AO_UART_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_AO_UART_REG5, ((uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_AO_UART_REG5, 1, 23, 1);
} else {
aml_set_reg32_mask(clks[i],(1<<8));
}
clk_flag[i] = 0;
printk(KERN_INFO "clk %s(%x) on\n", clks_name[i], clks[i]);
}
#ifdef M6_TV_CLK_DEBUG
if (clk_aud_23)
aml_set_reg32_mask(P_HHI_AUD_CLK_CNTL,(1<<23));
if (clk_vdec_24)
aml_set_reg32_mask(P_HHI_VDEC_CLK_CNTL,(1<<24));
#endif
}
} else {
for (i = 0; i < CLK_COUNT; i++) {
if ((clks[i] == P_HHI_VID_CLK_CNTL)||(clks[i] == P_HHI_VIID_CLK_CNTL)) {
clk_flag[i] = aml_get_reg32_bits(clks[i], 19, 2);
if (clk_flag[i]) {
aml_clr_reg32_mask(clks[i], (1<<19)|(1<<20));
}
} else if (clks[i] == P_HHI_MPEG_CLK_CNTL) {
if (aml_read_reg32(clks[i]) & (1 << 8)) {
if(xtal_uart_rate_backup == 0){//if no early suspend supported
struct clk* sys_clk = clk_get_sys("xtal", NULL);
xtal_uart_rate_backup = clk_get_rate(sys_clk);
}
wait_uart_empty();
clk_flag[i] = 1;
aml_clr_reg32_mask(clks[i], (1 << 8)); // 24M
udelay(10);
aml_clr_reg32_mask(clks[i], (1 << 7)); // 24M
udelay(10);
aml_clr_reg32_mask(P_UART0_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_UART0_REG5, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_UART0_REG5, 1, 23, 1);
aml_clr_reg32_mask(P_UART1_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_UART1_REG5, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_UART1_REG5, 1, 23, 1);
aml_clr_reg32_mask(P_AO_UART2_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_AO_UART2_REG5, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_AO_UART2_REG5, 1, 23, 1);
aml_clr_reg32_mask(P_AO_UART_REG5, 0x7FFFFF);
aml_set_reg32_bits(P_AO_UART_REG5, ((xtal_uart_rate_backup / (115200 * 4)) - 1) & 0x7fffff, 0, 23);
aml_set_reg32_bits(P_AO_UART_REG5, 1, 23, 1);
}
}
#ifdef M6_TV_CLK_DEBUG
else if (clks[i] == P_HHI_AUD_CLK_CNTL) {
clk_flag[i] = aml_get_reg32_bits(clks[i], 8, 1) ? 1 : 0;
if (clk_flag[i]) {
aml_clr_reg32_mask(clks[i], (1 << 8));
}
clk_aud_23 = aml_get_reg32_bits(clks[i], 23, 1) ? 1 : 0;
if (clk_aud_23) {
aml_clr_reg32_mask(clks[i], (1 << 23));
}
}
else if (clks[i] == P_HHI_VDEC_CLK_CNTL) {
clk_flag[i] = aml_get_reg32_bits(clks[i], 8, 1) ? 1 : 0;
if (clk_flag[i]) {
aml_clr_reg32_mask(clks[i], (1 << 8));
}
clk_vdec_24 = aml_get_reg32_bits(clks[i], 24, 1) ? 1 : 0;
if (clk_vdec_24) {
aml_clr_reg32_mask(clks[i], (1 << 24));
}
}
else {
clk_flag[i] = aml_get_reg32_bits(clks[i], 8, 1) ? 1 : 0;
if (clk_flag[i]) {
aml_clr_reg32_mask(clks[i], (1 << 8));
}
}
#else
else {
clk_flag[i] = aml_get_reg32_bits(clks[i], 8, 1) ? 1 : 0;
if (clk_flag[i]) {
aml_clr_reg32_mask(clks[i], (1 << 8));
}
}
#endif
if (clk_flag[i]) {
printk(KERN_INFO "clk %s(%x) off\n", clks_name[i], clks[i]);
wait_uart_empty();
}
}
}