示例#1
0
/*============================================================================*/
void bldr_jump(u32 addr, u32 arg1, u32 arg2)
{
    platform_wdt_kick();

    /* disable preloader safe mode */
    platform_safe_mode(0, 0);

    apmcu_disable_dcache();
    apmcu_dcache_clean_invalidate();
    apmcu_dsb();
    apmcu_icache_invalidate();
    apmcu_disable_icache();
    apmcu_isb();
    apmcu_disable_smp();

    print("\n%s jump to 0x%x\n", MOD, addr);
    print("%s <0x%x>=0x%x\n", MOD, addr, *(u32*)addr);
    print("%s <0x%x>=0x%x\n", MOD, addr + 4, *(u32*)(addr + 4));

    jump(addr, arg1, arg2);
}
示例#2
0
void main(void)
{
#if !defined(CFG_MEM_PRESERVED_MODE)
    struct bldr_command_handler handler;
#endif

    blkdev_t *bootdev;
    u32 addr;
    char *name;

#if defined(CFG_SRAM_PRELOADER_MODE)
    //jump to mem preloader directly
    //mem_baseaddr is defined in link_sram_descriptor.ld
    addr = (u32) &mem_baseaddr;
    jump(addr, BOOT_ARGUMENT_ADDR, sizeof(boot_arg_t));
#else   //#if defined(CFG_SRAM_PRELOADER_MODE)

    #ifdef PL_PROFILING
    u32 profiling_time;
    profiling_time = 0;
    #endif

    //Change setting to improve L2 CACHE SRAM access stability
    //CACHE_MEM_DELSEL: 0x10200014
    //bit 3:0		l2data_delsel	Adjusts memory marco timing
    //change setting: default=0xA  new=0xB
    *(volatile unsigned int *)0x10200014 = 0xAAAB;

    addr = 0;
    bldr_pre_process();

#ifdef TINY_BOOTLOADER
    while(1);
#endif

#if !defined(CFG_MEM_PRESERVED_MODE)
    handler.priv = NULL;
    handler.attr = 0;
    handler.cb   = bldr_cmd_handler;

    #ifdef PL_PROFILING
    profiling_time = get_timer(0);
    #endif
    bldr_handshake(&handler);

    #ifdef PL_PROFILING
    printf("#T#bldr_hdshk=%d\n", get_timer(profiling_time));
    #endif
#endif

    if (NULL == (bootdev = blkdev_get(CFG_BOOT_DEV))) {
        print("%s can't find boot device(%d)\n", MOD, CFG_BOOT_DEV);
        goto error;
    }

#if defined(LOAD_NORMAL_BOOT_PRELOADER)
    #ifdef PL_PROFILING
    profiling_time = get_timer(0);
    #endif

    {
        volatile u32 cache_cfg;

        #define L2C_SIZE_CFG_OFF 5
        //enable L2 sram for DA
        cache_cfg = DRV_Reg(APMCUSYS_CONFIG_BASE);
        cache_cfg &= ~(0x7 << L2C_SIZE_CFG_OFF);
        DRV_WriteReg(APMCUSYS_CONFIG_BASE, cache_cfg);

        //enable audio sysram clk for DA
        *(volatile unsigned int *)(0x10000084) = 0x02000000;
    }

    addr = CFG_UBOOT_MEMADDR;
    printf("load preloader=0x%x\n",addr);
    if (bldr_load_part(PART_PRELOADER, bootdev, &addr) != 0)
        goto error;

    addr = 0x02007200;
    printf("memcpy preloader=0x%x\n", addr);
    memcpy((void *)addr,(void *) CFG_UBOOT_MEMADDR,(int) 0x18E00);
    #ifdef PL_PROFILING
    printf("#T#ld_lk=%d\n", get_timer(profiling_time));
    #endif

    addr = 0x02007500;
    apmcu_disable_dcache();
    apmcu_dcache_clean_invalidate();
    apmcu_dsb();
    apmcu_icache_invalidate();
    apmcu_disable_icache();
    apmcu_isb();
    apmcu_disable_smp();
    printf("jump to preloader=0x%x\n", addr);

//    while( *(volatile unsigned int *)(0x10001428) != 0x000000AA)  ;

    jump((u32) addr, BOOT_ARGUMENT_ADDR, sizeof(boot_arg_t));
#endif


#if CFG_LOAD_DSP_ROM
    /* DSP is no more available in MT6589/MT6583 */
#endif

#if CFG_LOAD_MD_FS
    #ifdef PL_PROFILING
    profiling_time = get_timer(0);
    #endif
    addr = CFG_USE_HEADER_MEMADDR;
    name = PART_BOOTIMG;
    if (bldr_load_part(name, bootdev, &addr) != 0)
        ;   //goto error;
        // MD_FS partition may be empty

    #ifdef PL_PROFILING
    printf("#T#ld_MDFS=%d\n", get_timer(profiling_time));
    #endif
#endif

#if CFG_LOAD_MD_ROM
    #ifdef PL_PROFILING
    profiling_time = get_timer(0);
    #endif
    addr = CFG_USE_HEADER_MEMADDR;
    name = PART_RECOVERY;
    if (bldr_load_part(name, bootdev, &addr) != 0)
        goto error;

    #ifdef PL_PROFILING
    printf("#T#ld_MDROM=%d\n", get_timer(profiling_time));
    #endif
#endif

#if CFG_LOAD_AP_ROM
    #ifdef PL_PROFILING
    profiling_time = get_timer(0);
    #endif
    addr = CFG_USE_HEADER_MEMADDR;
    name = PART_UBOOT;
    if (bldr_load_part(name, bootdev, &addr) != 0)
        goto error;

    #ifdef PL_PROFILING
    printf("#T#ld_APROM=%d\n", get_timer(profiling_time));
    #endif
#endif

#if CFG_LOAD_UBOOT
    #ifdef PL_PROFILING
    profiling_time = get_timer(0);
    #endif
    addr = CFG_UBOOT_MEMADDR;
    if (bldr_load_part(PART_UBOOT, bootdev, &addr) != 0)
        goto error;

    #ifdef PL_PROFILING
    printf("#T#ld_lk=%d\n", get_timer(profiling_time));
    #endif
#endif

    bldr_post_process();
    bldr_jump(addr, BOOT_ARGUMENT_ADDR, sizeof(boot_arg_t));

error:
    platform_error_handler();
#endif  //end of #if !defined(CFG_SRAM_PRELOADER_MODE)

}
void platform_post_init(void)
{
    boot_arg_t *bootarg;
    struct ram_console_buffer *ram_console;

    #ifdef PL_PROFILING
    u32 profiling_time;
    profiling_time = 0;
    #endif

    bootarg = (boot_arg_t*)BOOT_ARGUMENT_ADDR;

#if CFG_BATTERY_DETECT
    #ifdef PL_PROFILING
    profiling_time = get_timer(0);
    #endif
    /* normal boot to check battery exists or not */
    if (g_boot_mode == NORMAL_BOOT && !hw_check_battery() && usb_accessory_in()) {
        print("%s Wait for battery inserted...\n", MOD);
        /* disable pmic pre-charging led */
        pl_close_pre_chr_led();
        /* enable force charging mode */
        pl_charging(1);
        do {
            mdelay(300);
            /* check battery exists or not */
            if (hw_check_battery())
                break;
            /* kick all watchdogs */
            platform_wdt_all_kick();
        } while(1);
        /* disable force charging mode */
        pl_charging(0);
    }

    #ifdef PL_PROFILING
    printf("#T#bat_detc=%d\n", get_timer(profiling_time));
    #endif
#endif

#if !CFG_FPGA_PLATFORM
    #ifdef PL_PROFILING
    profiling_time = get_timer(0);
    #endif
    /* security check */
    sec_lib_read_secro();
    sec_boot_check();
    device_APC_dom_setup();

    #ifdef PL_PROFILING
    printf("#T#sec_init=%d\n", get_timer(profiling_time));
    #endif
#endif

/* Note that the powering on MD is AP CCCI's task.                       */
/* Because the following code is for MT6589,                             */
/* although CFG_MDJTAG_SWITCH should not be defined,                     */
/* we still disable the following code just in case                      */
#if 0
#if CFG_MDJTAG_SWITCH
    unsigned int md_pwr_con;

    /* md0 default power on and clock on */
    /* md1 default power on and clock off */

    /* ungate md1 */
    /* rst_b = 0 */
    md_pwr_con = DRV_Reg32(0x10006280);
    md_pwr_con &= ~0x1;
    DRV_WriteReg32(0x10006280, md_pwr_con);

    /* enable clksq2 for md1 */
    DRV_WriteReg32(0x10209000, 0x00001137);
    udelay(200);
    DRV_WriteReg32(0x10209000, 0x0000113f);

    /* rst_b = 1 */
    md_pwr_con = DRV_Reg32(0x10006280);
    md_pwr_con |= 0x1;
    DRV_WriteReg32(0x10006280, md_pwr_con);

    /* switch to MD legacy JTAG */
    /* this step is not essentially required */
#endif
#endif

/* Note that the triggering MD META modeis AP CCCI's task.               */
/* Because the following code is for MT6589,                             */
/* although CFG_MDMETA_DETECT should not be defined,                     */
/* we still disable the following code just in case                      */
#if 0
#if CFG_MDMETA_DETECT
    if (g_boot_mode == META_BOOT || g_boot_mode == ADVMETA_BOOT) {
	/* trigger md0 to enter meta mode */
        DRV_WriteReg32(0x20000010, 0x1);
	/* trigger md1 to enter meta mode */
        DRV_WriteReg32(0x30000010, 0x1);
    } else {
	/* md0 does not enter meta mode */
        DRV_WriteReg32(0x20000010, 0x0);
	/* md1 does not enter meta mode */
        DRV_WriteReg32(0x30000010, 0x0);
    }
#endif
#endif

#if CFG_RAM_CONSOLE
    ram_console = (struct ram_console_buffer *)RAM_CONSOLE_ADDR;

    if (ram_console->sig == RAM_CONSOLE_SIG) {
        print("%s ram_console->start=0x%x\n", MOD, ram_console->start);
        if (ram_console->start > RAM_CONSOLE_MAX_SIZE)
            ram_console->start = 0;

        ram_console->hw_status = g_rgu_status;

        print("%s ram_console(0x%x)=0x%x (boot reason)\n", MOD,
            ram_console->hw_status, g_rgu_status);
    }
#endif

#if defined(CFG_MEM_PRESERVED_MODE)
    //wake up core 1 and flush core 1 cache
    print("%s core1 flush start\n", MOD);
    bootup_slave_cpu();
    print("%s core1 flush done\n", MOD);
    //flush core 1 cache
    print("%s core0 flush start\n", MOD);
#if 0
    {
        u32 i;
        volatile u32 tmp;

        tmp = 1;
        // for verify cache flush, write in LK, flush in preloader
        do {
        }while(tmp);

        for (i=0;i<0x100;i=i+4)
        {
            *(volatile u32 *)(CFG_DRAM_ADDR + 0x120000 + i) = 0xFFFFFFFF;
        }
    }
#endif
    apmcu_dcache_clean_invalidate();
    print("%s core0 flush done\n", MOD);
//    while(1);
#endif //#if !defined(CFG_MEM_PRESERVED_MODE)

#if CFG_BOOT_ARGUMENT
    //set UART1 GPIO to mode5, MD
    mt_gpio_init_post(1);

    bootarg->magic = BOOT_ARGUMENT_MAGIC;
    bootarg->mode  = g_boot_mode;
    //efuse should use seclib_get_devinfo_with_index(),
    //no need check 3G in 72
    bootarg->e_flag = 0;
    bootarg->log_port = CFG_UART_LOG;
    bootarg->log_baudrate = CFG_LOG_BAUDRATE;
    bootarg->log_enable = (u8)log_status();
    bootarg->dram_rank_num = get_dram_rank_nr();
    get_dram_rank_size(bootarg->dram_rank_size);
    bootarg->boot_reason = g_boot_reason;
    bootarg->meta_com_type = (u32)g_meta_com_type;
    bootarg->meta_com_id = g_meta_com_id;
    bootarg->boot_time = get_timer(g_boot_time);

    print("\n%s boot reason: %d\n", MOD, g_boot_reason);
    print("%s boot mode: %d\n", MOD, g_boot_mode);
    print("%s META COM%d: %d\n", MOD, bootarg->meta_com_id, bootarg->meta_com_type);
    print("%s <0x%x>: 0x%x\n", MOD, &bootarg->e_flag, bootarg->e_flag);
    print("%s boot time: %dms\n", MOD, bootarg->boot_time);
#endif
}