/*
* Dispatch interrupts.
* XXX: This currently does not prioritize except in calling order. Eventually
* there should perhaps be a static map which defines, the IPs to be masked for
* a given IP.
*/
void
ar7240_irq_dispatch(struct pt_regs *regs)
{
int pending = read_c0_status() & read_c0_cause();
if (pending & CAUSEF_IP7)
do_IRQ(AR7240_CPU_IRQ_TIMER, regs);
else if (pending & CAUSEF_IP2)
ar7240_dispatch_pci_intr(regs);
else if (pending & CAUSEF_IP4)
do_IRQ(AR7240_CPU_IRQ_GE0, regs);
else if (pending & CAUSEF_IP5)
do_IRQ(AR7240_CPU_IRQ_GE1, regs);
else if (pending & CAUSEF_IP3)
do_IRQ(AR7240_CPU_IRQ_USB, regs);
else if (pending & CAUSEF_IP6)
ar7240_dispatch_misc_intr(regs);
/*
* Some PCI devices are write to clear. These writes are posted and might
* require a flush (r8169.c e.g.). Its unclear what will have more
* performance impact - flush after every interrupt or taking a few
* "spurious" interrupts. For now, its the latter.
*/
/*else
printk("spurious IRQ pending: 0x%x\n", pending);*/
}
/*
* Dispatch interrupts.
* XXX: This currently does not prioritize except in calling order. Eventually
* there should perhaps be a static map which defines, the IPs to be masked for
* a given IP.
*/
asmlinkage void plat_irq_dispatch(void)
{
int pending = read_c0_status() & read_c0_cause();
#if 0
if (!(pending & CAUSEF_IP7))
printk("%s: in irq dispatch \n", __func__);
#endif
if (pending & CAUSEF_IP7)
do_IRQ(AR7240_CPU_IRQ_TIMER);
else if (pending & CAUSEF_IP2) {
//printk("%s: 0x%x\n", __func__, ar7240_reg_rd(AR7240_PCIE_WMAC_INT_STATUS));
#ifdef CONFIG_WASP_SUPPORT
#ifdef CONFIG_PCI
if (unlikely(ar7240_reg_rd
(AR7240_PCIE_WMAC_INT_STATUS) & PCI_WMAC_INTR))
ar7240_dispatch_pci_intr();
else
#endif
do_IRQ(ATH_CPU_IRQ_WLAN);
#elif defined (CONFIG_MACH_HORNET)
do_IRQ(ATH_CPU_IRQ_WLAN);
#else
ar7240_dispatch_pci_intr();
#endif
}
else if (pending & CAUSEF_IP4)
do_IRQ(AR7240_CPU_IRQ_GE0);
else if (pending & CAUSEF_IP5)
do_IRQ(AR7240_CPU_IRQ_GE1);
else if (pending & CAUSEF_IP3)
do_IRQ(AR7240_CPU_IRQ_USB);
else if (pending & CAUSEF_IP6)
ar7240_dispatch_misc_intr();
/*
* Some PCI devices are write to clear. These writes are posted and might
* require a flush (r8169.c e.g.). Its unclear what will have more
* performance impact - flush after every interrupt or taking a few
* "spurious" interrupts. For now, its the latter.
*/
/*else
printk("spurious IRQ pending: 0x%x\n", pending);*/
}