void ar7240_gpio_config_int(int gpio,
ar7240_gpio_int_type_t type,
ar7240_gpio_int_pol_t polarity)
{
u32 val;
/*
* allow edge sensitive/rising edge too
*/
if (type == INT_TYPE_LEVEL) {
/* level sensitive */
ar7240_reg_rmw_set(AR7240_GPIO_INT_TYPE, (1 << gpio));
}
else {
/* edge triggered */
val = ar7240_reg_rd(AR7240_GPIO_INT_TYPE);
val &= ~(1 << gpio);
ar7240_reg_wr(AR7240_GPIO_INT_TYPE, val);
}
if (polarity == INT_POL_ACTIVE_HIGH) {
ar7240_reg_rmw_set (AR7240_GPIO_INT_POLARITY, (1 << gpio));
}
else {
val = ar7240_reg_rd(AR7240_GPIO_INT_POLARITY);
val &= ~(1 << gpio);
ar7240_reg_wr(AR7240_GPIO_INT_POLARITY, val);
}
ar7240_reg_rmw_set(AR7240_GPIO_INT_ENABLE, (1 << gpio));
}
void gpio_config(void){
/* disable the CLK_OBS on GPIO_4 and set GPIO4 as input */
ar7240_reg_rmw_clear(GPIO_OE_ADDRESS, (1 << 4));
ar7240_reg_rmw_clear(GPIO_OUT_FUNCTION1_ADDRESS, GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK);
ar7240_reg_rmw_set(GPIO_OUT_FUNCTION1_ADDRESS, GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(0x80));
ar7240_reg_rmw_set(GPIO_OE_ADDRESS, (1 << 4));
}
void glzt_set_gpio_to_iis(void)
{
/* Set GPIO I2S Enables */
ar7240_reg_rmw_set(AR7240_GPIO_FUNCTIONS,
(AR7240_GPIO_FUNCTION_SPDIF_EN |
AR7240_GPIO_FUNCTION_I2S_MCKEN |
AR7240_GPIO_FUNCTION_I2S0_EN|
AR7240_GPIO_FUNCTION_I2S_GPIO_18_22_EN
));
ar7240_reg_rmw_set(AR7240_GPIO_FUNCTION_2, (1<<2)); //Enables the SPDIF output on GPIO2
}
static void
ar7240_pci_irq_enable(unsigned int irq)
{
#ifdef CONFIG_PERICOM
/* Copied from NetBSD */
if (irq == AR7240_PCI_IRQ_DEV0) {
ar7240_reg_rmw_set(AR7240_PCI_INT_MASK, AR7240_PCI_INT_B_L);
} else {
ar7240_reg_rmw_set(AR7240_PCI_INT_MASK, AR7240_PCI_INT_C_L);
}
#else
ar7240_reg_rmw_set(AR7240_PCI_INT_MASK, AR7240_PCI_INT_A_L);
#endif /* CONFIG_PERICOM */
}
void check_sysMode(unsigned long nothing)
{
int system_mode;
if (ar7240_gpio_in_val(SYS_MODE_GPIO_1)
&& ar7240_gpio_in_val(SYS_MODE_GPIO_2)) // AP
{
system_mode = SYSTEM_MODE_AP;
}
else if (!ar7240_gpio_in_val(SYS_MODE_GPIO_1)
&& ar7240_gpio_in_val(SYS_MODE_GPIO_2)) // APC
{
system_mode = SYSTEM_MODE_APC_ROUTER;
}
else // 3G
{
system_mode = SYSTEM_MODE_3G_ROUTER;
}
if (g_sysMode != system_mode && !g_isSoftSysModeEnable)
{
//reboot router
printk("rebooting...\n");
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_FULL_CHIP);
return;
}
mod_timer(&sysMode_timer, jiffies + 1 * HZ);
}
void glzt_set_gpio_to_l3(void)
{
/*Set GPIO control wm8978 */
ar7240_reg_rmw_set(RST_RESET,AR7240_RESET_I2S|AR7240_RESET_PCI_CORE);
udelay(500);
ar7240_reg_wr(AR7240_GPIO_OE,(IIS_CONTROL_CSB|IIS_CONTROL_SDIN|IIS_CONTROL_SCLK));
}
u32
ar9285DisableJtag(void)
{
/*
* Disable ar9285's JTAG access. Else, gpio 0 - 4 will be used
* by the jtag. This does NOT affect board's JTAG interface
*/
ar7240_reg_rmw_set(AR9285_GPIO_IN_ENABLE, AR9285_GPIO_JTAG_DISABLE);
}
void
ar7240_gpio_out_val(int gpio, int val)
{
if (val & 0x1) {
ar7240_reg_rmw_set(AR7240_GPIO_OUT, (1 << gpio));
}
else {
ar7240_reg_rmw_clear(AR7240_GPIO_OUT, (1 << gpio));
}
}
static void
ar7240_misc_irq_enable(unsigned int irq)
{
#if 0
vpk("%s: %u ", __func__, irq);
vps("%s\n", __builtin_return_address(0));
#endif
ar7240_reg_rmw_set(AR7240_MISC_INT_MASK,
(1 << (irq - AR7240_MISC_IRQ_BASE)));
}
unsigned long flash_init(void)
{
#ifndef CONFIG_WASP
#ifdef ATH_SST_FLASH
ar7240_reg_wr_nf(AR7240_SPI_CLOCK, 0x3);
ar7240_spi_flash_unblock();
ar7240_reg_wr(AR7240_SPI_FS, 0);
#else
ar7240_reg_wr_nf(AR7240_SPI_CLOCK, 0x43);
#endif
#endif
ar7240_reg_rmw_set(AR7240_SPI_FS, 1);
ath_spi_read_id();
ar7240_reg_rmw_clear(AR7240_SPI_FS, 1);
/*
* hook into board specific code to fill flash_info
*/
return (flash_get_geom(&flash_info[0]));
}
int ag7240_enet_initialize(bd_t * bis){
struct eth_device *dev[CFG_AG7240_NMACS];
u32 mask, mac_h, mac_l;
int i;
//printf("ag934x_enet_initialize...\n");
/*
if(is_ar933x() && (ar7240_reg_rd(AR7240_RESET)!=0)){
ar7240_reg_wr(AR7240_RESET,0);
}
if(is_ar933x()) //Turn on LED
ar7240_reg_wr(AR7240_GPIO_BASE + 0x28 , ar7240_reg_rd(AR7240_GPIO_BASE + 0x28) | (0xF8));
*/
for(i = 0;i < CFG_AG7240_NMACS;i++){
if((dev[i] = (struct eth_device *)malloc(sizeof(struct eth_device))) == NULL){
//puts("malloc failed\n");
return(0);
}
if((ag7240_macs[i] = (ag7240_mac_t *)malloc(sizeof(ag7240_mac_t))) == NULL){
//puts("malloc failed\n");
return(0);
}
memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
memset(dev[i], 0, sizeof(dev[i]));
sprintf(dev[i]->name, "eth%d", i);
ag7240_get_ethaddr(dev[i]);
ag7240_macs[i]->mac_unit = i;
ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE ;
ag7240_macs[i]->dev = dev[i];
dev[i]->iobase = 0;
dev[i]->init = ag7240_clean_rx;
dev[i]->halt = ag7240_halt;
dev[i]->send = ag7240_send;
dev[i]->recv = ag7240_recv;
dev[i]->priv = (void *)ag7240_macs[i];
}
for(i = 0;i < CFG_AG7240_NMACS;i++){
eth_register(dev[i]);
#if(CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);
#endif
ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);
if(!i){
mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY);
if(is_ar7241() || is_ar7242() || is_wasp()){
mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;
}
//printf(" wasp reset mask:%x \n",mask);
ar7240_reg_rmw_set(AR7240_RESET, mask);
udelay(1000 * 100);
ar7240_reg_rmw_clear(AR7240_RESET, mask);
udelay(1000 * 100);
udelay(10 * 1000);
}
ag7240_hw_start(ag7240_macs[i]);
ag7240_setup_fifos(ag7240_macs[i]);
udelay(100 * 1000);
//unsigned char *mac = dev[i]->enetaddr;
//printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);
/* if using header for register configuration, we have to */
/* configure s26 register after frame transmission is enabled */
if(ag7240_macs[i]->mac_unit == 0){ /* WAN Phy */
#ifdef CONFIG_AR7242_S16_PHY
if(is_ar7242() || is_wasp()){
athrs16_reg_init();
} else
#endif
{
#ifdef CFG_ATHRS17_PHY
athrs17_reg_init();
#endif
#ifdef CFG_ATHRS26_PHY
athrs26_reg_init();
#endif
#ifdef CFG_ATHRS27_PHY
//printf("s27 reg init \n");
athrs27_reg_init();
#endif
#ifdef CONFIG_F1E_PHY
//printf("F1Phy reg init \n");
athr_reg_init();
#endif
#ifdef CONFIG_VIR_PHY
//printf("VIRPhy reg init \n");
athr_vir_reg_init();
#endif
#ifdef CONFIG_F2E_PHY
//printf("F2Phy reg init \n");
athr_reg_init();
#endif
}
} else {
#ifdef CFG_ATHRS26_PHY
athrs26_reg_init_lan();
#endif
#ifdef CFG_ATHRS27_PHY
//printf("s27 reg init lan \n");
athrs27_reg_init_lan();
#endif
}
ag7240_phy_setup(ag7240_macs[i]->mac_unit);
//printf("%s up\n",dev[i]->name);
}
return(1);
}
static int ag7240_check_link(ag7240_mac_t *mac){
int link = 0, duplex = 0, speed = 0;
char *s;
s = getenv("stdin");
ag7240_phy_link(mac->mac_unit, &link);
ag7240_phy_duplex(mac->mac_unit, &duplex);
ag7240_phy_speed(mac->mac_unit, &speed);
mac->link = link;
if(!mac->link){
if((s != NULL) && (strcmp(s, "nc") != 0)){
printf("Link down: %s\n", mac->dev->name);
}
return(0);
}
switch(speed){
case _1000BASET:
ag7240_set_mac_if(mac, 1);
ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
if(is_ar7242() && (mac->mac_unit == 0)){
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x1c000000);
}
#ifdef CONFIG_F1E_PHY
if(is_wasp() && (mac->mac_unit == 0)){
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x0e000000);
}
#elif CONFIG_VIR_PHY
if(is_wasp() && (mac->mac_unit == 0)){
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x82000000);
ar7240_reg_wr(AG7240_ETH_CFG, 0x000c0001);
}
#else
if(is_wasp() && (mac->mac_unit == 0) && !is_f2e()){
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x06000000);
}
#endif
if(is_wasp() && mac->mac_unit == 0 && is_f1e() ){
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RXD_DELAY);
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RDV_DELAY);
}
break;
case _100BASET:
ag7240_set_mac_if(mac, 0);
ag7240_set_mac_speed(mac, 1);
ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
if((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e()){
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG, 0x0101);
}
if(is_wasp() && mac->mac_unit == 0 && is_f1e()){
ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RXD_DELAY);
ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RDV_DELAY);
}
break;
case _10BASET:
ag7240_set_mac_if(mac, 0);
ag7240_set_mac_speed(mac, 0);
ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
if((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e()){
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1616);
}
if(is_wasp() && mac->mac_unit == 0 && is_f1e()){
ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RXD_DELAY);
ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RDV_DELAY);
}
if(is_f2e()){
ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RMII_HISPD_GE0);
}
break;
default:
if((s != NULL) && (strcmp(s, "nc") != 0)){
printf("## Error: invalid speed detected\n");
}
return(0);
}
if(mac->link && (duplex == mac->duplex) && (speed == mac->speed)){
return(1);
}
mac->duplex = duplex;
mac->speed = speed;
if((s != NULL) && (strcmp(s, "nc") != 0)){
printf("Ethernet mode (duplex/speed): %d/%d Mbps\n", duplex, speed);
}
ag7240_set_mac_duplex(mac, duplex);
return(1);
}
int pci_init_board(void){
uint32_t cmd = 0, reg_val;
reg_val = ar7240_reg_rd(0xb804006c);
ar7240_reg_wr(0xb804006c, reg_val | 2);
ar7240_reg_wr(0xb804000c, 1 << 2);
pci_udelay(100000);
/*
if((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0){
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x20) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0)
);
} else {
printf("%s: PCIe PLL not set for 40MHz refclk\n", __func__);
}
*/
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE); // core in reset
pci_udelay(10000);
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE_PHY);// phy in reset
pci_udelay(10000);
ar7240_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog in reset
pci_udelay(10000);
ar7240_reg_wr(0x180f0000, 0x1ffc0); // ltssm is disabled
pci_udelay(100);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 0); // End point in reset
pci_udelay(100000);
//ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY);
/*
if((ar7240_reg_rd(AR7240_REV_ID) & 0xf) == 0){
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1)
);
pci_udelay(10000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(0)
);
pci_udelay(1000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
ar7240_reg_rd(AR934X_PCIE_PLL_CONFIG) &
(~PCIE_PLL_CONFIG_BYPASS_SET(1))
);
pci_udelay(1000);
} else {
*/
ar7240_reg_wr_nf(0xb8116c04, (0x0 << 30) | (0x4 << 26) | (0x32 << 19) | (1 << 16) | (3 << 13) | (0x1e << 7));
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8116c08, (6 << 23));
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8050010, 0x40010800);
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8050014, 0xc013fffe);
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8050018, 0x00138000);
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8050010, 0x00010800);
pci_udelay(100000);
ar7240_reg_wr_nf(0xb8050010, 0x00000800);
pci_udelay(10000);
/*
}
*/
ar7240_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY); // phy out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE); // core out of reset
pci_udelay(1000);
cmd = PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER |
PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY |
PCI_COMMAND_SERR |
PCI_COMMAND_FAST_BACK;
ar7240_local_write_config(PCI_COMMAND, 4, cmd); // pci cmd reg init
ar7240_local_write_config(0x20, 4, 0x1ff01000); // membase setting
ar7240_local_write_config(0x24, 4, 0x1ff01000); // prefetch membase setting
//if((is_ar7241() || is_ar7242() || is_wasp())){
ar7240_reg_wr(0x180f0000, 0x1ffc1); // ltssm enable
//} else {
// ar7240_reg_wr(0x180f0000, 0x1);
//}
pci_udelay(100000);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 4); // EP out of reset
//pci_udelay(100000);
/*
* Delay increased from 100 to 1000, so as to
* get the correct status from PCI LCL RESET register
*/
// pci_udelay(100000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
//if(((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0){
// printf("## Error: PCIe WLAN Module not found!\n");
//}
//plat_dev_init();
return(0);
}
ssize_t ar7240_i2s_read(struct file * filp, char __user * buf,size_t count, loff_t * f_pos)//gl-inet
{
#define prev_tail(t) ({ (t == 0) ? (NUM_DESC - 1) : (t - 1); })
#define next_tail(t) ({ (t == (NUM_DESC - 1)) ? 0 : (t + 1); })
uint8_t *data;
//ssize_t retval;
unsigned long retval;
struct ar7240_i2s_softc *sc = &sc_buf_var;
i2s_dma_buf_t *dmabuf = &sc->sc_rbuf;
i2s_buf_t *scbuf;
ar7240_mbox_dma_desc *desc;
unsigned int byte_cnt, mode = 1, offset = 0, tail = dmabuf->tail;
unsigned long desc_p;
int need_start = 0;
byte_cnt = count;
if (sc->ropened < 2) {
ar7240_reg_rmw_set(MBOX_INT_ENABLE, MBOX0_TX_DMA_COMPLETE);
need_start = 1;
}
sc->ropened = 2;
scbuf = dmabuf->db_buf;
desc = dmabuf->db_desc;
desc_p = (unsigned long) dmabuf->db_desc_p;
data = scbuf[0].bf_vaddr;
desc_p += tail * sizeof(ar7240_mbox_dma_desc);
while (byte_cnt && !desc[tail].OWN) {
if (byte_cnt >= I2S_BUF_SIZE) {
desc[tail].length = I2S_BUF_SIZE;
byte_cnt -= I2S_BUF_SIZE;
} else {
desc[tail].length = byte_cnt;
byte_cnt = 0;
}
//ar7240_dma_cache_sync(scbuf[tail].bf_vaddr, desc[tail].length);//gl-inet
dma_cache_sync(NULL, scbuf[tail].bf_vaddr, desc[tail].length, DMA_FROM_DEVICE);//gl-inet
desc[tail].rsvd2 = 0;//gl-inet
retval = copy_to_user((buf + offset), (scbuf[tail].bf_vaddr), I2S_BUF_SIZE);
if (retval)
return retval;
desc[tail].BufPtr = (unsigned int) scbuf[tail].bf_paddr;
desc[tail].OWN = 1;
tail = next_tail(tail);
offset += I2S_BUF_SIZE;
}
dmabuf->tail = tail;
if (need_start) {
ar7240_i2sound_dma_desc((unsigned long) desc_p, mode);
if (filp) {
ar7240_i2sound_dma_start(mode);
}
} else if (!sc->rpause) {
ar7240_i2sound_dma_resume(mode);
}
return offset;
}
ssize_t ar7240_i2s_write(struct file * filp, const char __user * buf,
size_t count, loff_t * f_pos, int resume)
{
#define prev_tail(t) ({ (t == 0) ? (NUM_DESC - 1) : (t - 1); })
#define next_tail(t) ({ (t == (NUM_DESC - 1)) ? 0 : (t + 1); })
// uint8_t *data;
ssize_t retval;
int byte_cnt, offset, need_start = 0;
int mode = 0;
struct ar7240_i2s_softc *sc = &sc_buf_var;
i2s_dma_buf_t *dmabuf = &sc->sc_pbuf;
i2s_buf_t *scbuf;
ar7240_mbox_dma_desc *desc;
int tail = dmabuf->tail;
unsigned long desc_p;
int data_len = 0;
I2S_LOCK(sc);
byte_cnt = count;
//printk("count:%d\n",count);
//printk("byte_cnt:%d\n",byte_cnt);
if (sc->popened < 2) {
ar7240_reg_rmw_set(MBOX_INT_ENABLE, MBOX0_RX_DMA_COMPLETE | RX_UNDERFLOW);
need_start = 1;
}
sc->popened = 2;
scbuf = dmabuf->db_buf;
desc = dmabuf->db_desc;
desc_p = (unsigned long) dmabuf->db_desc_p;
offset = 0;
//data = scbuf[0].bf_vaddr;
desc_p += tail * sizeof(ar7240_mbox_dma_desc);
while (byte_cnt && !desc[tail].OWN) {
if (byte_cnt >= I2S_BUF_SIZE) {
desc[tail].length = I2S_BUF_SIZE;
byte_cnt -= I2S_BUF_SIZE;
data_len = I2S_BUF_SIZE;
} else {
desc[tail].length = byte_cnt;
data_len = byte_cnt;
byte_cnt = 0;
}
if(!filp)
{
memcpy(scbuf[tail].bf_vaddr, buf + offset, data_len);
}
else
{
retval = copy_from_user(scbuf[tail].bf_vaddr, buf + offset, data_len);
if (retval)
return retval;
}
ar7240_cache_inv(scbuf[tail].bf_vaddr, desc[tail].length);
dma_cache_sync(NULL, scbuf[tail].bf_vaddr, desc[tail].length, DMA_TO_DEVICE);
desc[tail].BufPtr = (unsigned int) scbuf[tail].bf_paddr;
desc[tail].OWN = 1;
tail = next_tail(tail);
offset += data_len;
}
dmabuf->tail = tail;
if (need_start) {
ar7240_i2sound_dma_desc((unsigned long) desc_p, mode);
ar7240_i2sound_dma_start(mode);
}
else if (!sc->ppause) {
ar7240_i2sound_dma_resume(mode);
}
// if (resume)
// ar7240_i2sound_dma_resume(mode);
I2S_UNLOCK(sc);
//all_data+=(count - byte_cnt);
//printk("all_data:%ld\n",all_data);
//glzt_msleep(10);
return count - byte_cnt;
}
static long ar7240_i2s_ioctl(struct file *filp,unsigned int cmd, unsigned long arg)
{
#define AR7240_STEREO_CONFIG_DEFAULT (AR7240_STEREO_CONFIG_SPDIF_ENABLE| \
AR7240_STEREO_CONFIG_ENABLE| \
AR7240_STEREO_CONFIG_RESET| \
AR7240_STEREO_CONFIG_MIC_WORD_SIZE| \
AR7240_STEREO_CONFIG_MODE(0)| \
AR7240_STEREO_CONFIG_PSEDGE(2) | \
AR7240_STEREO_CONFIG_SAMPLE_CNT_CLEAR_TYPE| \
AR7240_STEREO_CONFIG_MASTER) //gl-inet
int data, mask = 0, cab = 0, cab1 = 0, j, st_cfg = 0;
long val;
struct ar7240_i2s_softc *sc = &sc_buf_var;
i2s_dma_buf_t *dmabuf;
if (filp->f_mode & FMODE_READ) {
dmabuf = &sc->sc_rbuf;
} else {
dmabuf = &sc->sc_pbuf;
}
//start oss
#if 1
//case 8:
st_cfg = (AR7240_STEREO_CONFIG_DEFAULT |
AR7240_STEREO_CONFIG_DATA_WORD_SIZE(AR7240_STEREO_WS_8B)
);
cab1 = SPDIF_CONFIG_SAMP_SIZE(SPDIF_S_8_16);
#endif
#if 0
//case 16:
st_cfg = (AR7240_STEREO_CONFIG_DEFAULT |
AR7240_STEREO_CONFIG_PCM_SWAP |
AR7240_STEREO_CONFIG_DATA_WORD_SIZE(AR7240_STEREO_WS_16B)
);
cab1 = SPDIF_CONFIG_SAMP_SIZE(SPDIF_S_8_16);
#endif
#if 0
//case 24:
st_cfg = (AR7240_STEREO_CONFIG_DEFAULT |
AR7240_STEREO_CONFIG_PCM_SWAP |
AR7240_STEREO_CONFIG_DATA_WORD_SIZE(AR7240_STEREO_WS_24B) |
AR7240_STEREO_CONFIG_I2S_32B_WORD
);
cab1 = SPDIF_CONFIG_SAMP_SIZE(SPDIF_S_24_32);
#endif
#if 0
//case 32:
st_cfg = (AR7240_STEREO_CONFIG_DEFAULT |
AR7240_STEREO_CONFIG_PCM_SWAP |
AR7240_STEREO_CONFIG_DATA_WORD_SIZE(AR7240_STEREO_WS_32B) |
AR7240_STEREO_CONFIG_I2S_32B_WORD
);
cab1 = SPDIF_CONFIG_SAMP_SIZE(SPDIF_S_24_32);
#endif
ar7240_reg_wr(AR7240_STEREO_CONFIG, (st_cfg | AR7240_STEREO_CONFIG_RESET));
udelay(100);
ar7240_reg_rmw_clear(AR7240_STEREO_CONFIG,AR7240_STEREO_CONFIG_RESET);
ar7240_reg_wr(AR7240_STEREO_CONFIG, st_cfg);
for (j = 0; j < NUM_DESC; j++) {
dmabuf->db_desc[j].Ca[1] |= cab1;
dmabuf->db_desc[j].Cb[1] |= cab1;
}
wm8978_volume = ((50 & 0xff)*32)/100;
wm8978_write_reg(52,((1<<8)|wm8978_volume));
wm8978_write_reg(53,((1<<8)|wm8978_volume));
switch (cmd) {
case SNDCTL_DSP_SETFMT:
printk("cmd:SNDCTL_DSP_SETFMT,未用\n");
get_user(val, (long *) arg);
/*
if (val & AUDIO_FMT_MASK) {
audio_fmt = val;
break;
} else
return -EINVAL;
*/
case SNDCTL_DSP_CHANNELS:
printk("cmd:SNDCTL_DSP_CHANNELS\n");
case SNDCTL_DSP_STEREO:
printk("cmd:SNDCTL_DSP_STEREO\n");
get_user(data, (long *) arg);
audio_channels = data;
printk("set audio_channels:%d\n",audio_channels);
/* For MONO */
if (data != 2) {
ar7240_reg_rmw_set(AR7240_STEREO_CONFIG, MONO);
} else {
ar7240_reg_rmw_clear(AR7240_STEREO_CONFIG, MONO);
}
return 0;
/*
get_user(val, (long *) arg);
if (cmd == SNDCTL_DSP_STEREO)
val = val ? 2 : 1;
if (val != 1 && val != 2)
return -EINVAL;
audio_channels = val;
break;
*/
case SOUND_PCM_READ_CHANNELS:
printk("cmd:SOUND_PCM_READ_CHANNELS\n");
put_user(audio_channels, (long *) arg);
printk("get audio_channels:%d\n",audio_channels);
break;
case SNDCTL_DSP_SPEED:
printk("cmd:SNDCTL_DSP_SPEED\n");
get_user(val, (long *) arg);
printk("set rate:%d\n",val);
audio_rate = val;
//val = audio_set_dsp_speed(val);
switch (val) {
case 44100:
//ar7240_i2s_clk(0x0a47f028, 0x2383);
//cab = SPDIF_CONFIG_SAMP_FREQ(SPDIF_SAMP_FREQ_44);
//cab1 = SPDIF_CONFIG_ORG_FREQ(SPDIF_ORG_FREQ_44);
//ar7240_reg_wr(AR7240_STEREO_CLK_DIV,0xec330);//gl-inet
ar7240_reg_wr(AR7240_STEREO_CLK_DIV,((0x11 << 16) + 0xb6b0));//gl-inet 44100kHz
break;
case 48000:
//ar7240_i2s_clk(0x03c9f02c, 0x2383);
//cab = SPDIF_CONFIG_SAMP_FREQ(SPDIF_SAMP_FREQ_48);
//cab1 = SPDIF_CONFIG_ORG_FREQ(SPDIF_ORG_FREQ_48);
//ar7240_reg_wr(AR7240_STEREO_CLK_DIV,0xd9013);//gl-inet
ar7240_reg_wr(AR7240_STEREO_CLK_DIV,((0x10 << 16) + 0x4600));//gl-inet 48000kHz
break;
default:
printk(KERN_CRIT "Freq %d not supported \n",data);
return -ENOTSUPP;
}
for (j = 0; j < NUM_DESC; j++) {
dmabuf->db_desc[j].Ca[0] |= cab;
dmabuf->db_desc[j].Cb[0] |= cab;
dmabuf->db_desc[j].Ca[1] |= cab1;
dmabuf->db_desc[j].Cb[1] |= cab1;
}
if (val < 0)
return -EINVAL;
put_user(val, (long *) arg);
break;
case SOUND_PCM_READ_RATE:
printk("cmd:SOUND_PCM_READ_RATE\n");
put_user(audio_rate, (long *) arg);
break;
case SNDCTL_DSP_GETFMTS:
printk("cmd:SNDCTL_DSP_GETFMTS,返回FMT掩码\n");
put_user(AUDIO_FMT_MASK, (long *) arg);
break;
case SNDCTL_DSP_GETBLKSIZE:
printk("cmd:SNDCTL_DSP_GETBLKSIZE\n");
if(filp->f_mode & FMODE_WRITE)
//return put_user(audio_fragsize, (long *) arg);
//else
//return put_user(audio_fragsize, (int *) arg);
break;
case SNDCTL_DSP_SETFRAGMENT:
printk("cmd:SNDCTL_DSP_SETFRAGMENT\n");
/*
if (file->f_mode & FMODE_WRITE) {
if (output_stream.buffers)
return -EBUSY;
get_user(val, (long *) arg);
audio_fragsize = 1 << (val & 0xFFFF);
if (audio_fragsize < 16)
audio_fragsize = 16;
if (audio_fragsize > 16384)
audio_fragsize = 16384;
audio_nbfrags = (val >> 16) & 0x7FFF;
if (audio_nbfrags < 2)
audio_nbfrags = 2;
if (audio_nbfrags * audio_fragsize > 128 * 1024)
audio_nbfrags = 128 * 1024 / audio_fragsize;
if (audio_setup_buf(&output_stream))
return -ENOMEM;
}
if (file->f_mode & FMODE_READ) {
if (input_stream.buffers)
return -EBUSY;
get_user(val, (int *) arg);
audio_fragsize = 1 << (val & 0xFFFF);
if (audio_fragsize < 16)
audio_fragsize = 16;
if (audio_fragsize > 16384)
audio_fragsize = 16384;
audio_nbfrags = (val >> 16) & 0x7FFF;
if (audio_nbfrags < 2)
audio_nbfrags = 2;
if (audio_nbfrags * audio_fragsize > 128 * 1024)
audio_nbfrags = 128 * 1024 / audio_fragsize;
if (audio_setup_buf(&input_stream))
return -ENOMEM;
}
*/
break;
case SNDCTL_DSP_SYNC:
printk("cmd:SNDCTL_DSP_SYNC,audio_sync(file),同步一下音频数据\n");
//return audio_sync(file);
break;
case SNDCTL_DSP_GETOSPACE:
{
printk("cmd:SNDCTL_DSP_GETOSPACE\n");
/*
audio_stream_t *s = &output_stream;
audio_buf_info *inf = (audio_buf_info *) arg;
int err = access_ok(VERIFY_WRITE, inf, sizeof(*inf));
int i;
int frags = 0, bytes = 0;
if (err)
return err;
for (i = 0; i < s->nbfrags; i++) {
if (atomic_read(&s->buffers[i].sem.count) > 0) {
if (s->buffers[i].size == 0) frags++;
bytes += s->fragsize - s->buffers[i].size;
}
}
put_user(frags, &inf->fragments);
put_user(s->nbfrags, &inf->fragstotal);
put_user(s->fragsize, &inf->fragsize);
put_user(bytes, &inf->bytes);
*/
break;
}
case SNDCTL_DSP_GETISPACE:
{
printk("cmd:SNDCTL_DSP_GETISPACE\n");
/*
audio_stream_t *s = &input_stream;
audio_buf_info *inf = (audio_buf_info *) arg;
int err = access_ok(VERIFY_WRITE, inf, sizeof(*inf));
int i;
int frags = 0, bytes = 0;
if (!(file->f_mode & FMODE_READ))
return -EINVAL;
if (err)
return err;
for(i = 0; i < s->nbfrags; i++){
if (atomic_read(&s->buffers[i].sem.count) > 0)
{
if (s->buffers[i].size == s->fragsize)
frags++;
bytes += s->buffers[i].size;
}
}
put_user(frags, &inf->fragments);
put_user(s->nbfrags, &inf->fragstotal);
put_user(s->fragsize, &inf->fragsize);
put_user(bytes, &inf->bytes);
*/
break;
}
case SNDCTL_DSP_RESET:
printk("cmd:SNDCTL_DSP_RESET\n");
data = arg;
ar7240_i2sound_dma_resume(data);
if (data) {
sc->rpause = 0;
}else {
sc->ppause = 0;
}
return 0;
/*
if (file->f_mode & FMODE_READ) {
audio_clear_buf(&input_stream);
}
if (file->f_mode & FMODE_WRITE) {
audio_clear_buf(&output_stream);
}
return 0;
*/
case SNDCTL_DSP_NONBLOCK:
printk("cmd:SNDCTL_DSP_NONBLOCK\n");
filp->f_flags |= O_NONBLOCK;
return 0;
case SNDCTL_DSP_POST:printk("cmd:SNDCTL_DSP_POST\n");
case SNDCTL_DSP_SUBDIVIDE:printk("cmd:SNDCTL_DSP_SUBDIVIDE\n");
case SNDCTL_DSP_GETCAPS:printk("cmd:SNDCTL_DSP_GETCAPS\n");
case SNDCTL_DSP_GETTRIGGER:printk("cmd:SNDCTL_DSP_GETTRIGGER\n");
case SNDCTL_DSP_SETTRIGGER:printk("cmd:SNDCTL_DSP_SETTRIGGER\n");
case SNDCTL_DSP_GETIPTR:printk("cmd:SNDCTL_DSP_GETIPTR\n");
case SNDCTL_DSP_GETOPTR:printk("cmd:SNDCTL_DSP_GETOPTR\n");
case SNDCTL_DSP_MAPINBUF:printk("cmd:SNDCTL_DSP_MAPINBUF\n");
case SNDCTL_DSP_MAPOUTBUF:printk("cmd:SNDCTL_DSP_MAPOUTBUF\n");
case SNDCTL_DSP_SETSYNCRO:printk("cmd:SNDCTL_DSP_SETSYNCRO\n");
case SNDCTL_DSP_SETDUPLEX:printk("cmd:SNDCTL_DSP_SETDUPLEX\n");
return -ENOSYS;
default:
return smdk2410_mixer_ioctl(filp, cmd, arg);
}
return 0;
//end oss
/*
if (ioctl(audio, I2S_DSIZE, hdr.bit_p_spl) < 0) {
perror("I2S_DSIZE");
}
if (ioctl(audio, I2S_FREQ, hdr.sample_fq) < 0) {
perror("I2S_FREQ");
}
*/
#if 0
switch (cmd) {
case I2S_PAUSE:
data = arg;
ar7240_i2sound_dma_pause(data);
if (data) {
sc->rpause = 1;
} else {
sc->ppause = 1;
}
return 0;
case I2S_RESUME:
data = arg;
ar7240_i2sound_dma_resume(data);
if (data) {
sc->rpause = 0;
}else {
sc->ppause = 0;
}
return 0;
case I2S_VOLUME:
data = arg;
if (data < 15) {
if (data < 0) {
mask = 0xf;
} else {
mask = (~data) & 0xf;
mask = mask | 0x10;
}
} else {
if (data <= 22) {
if (data == 15) {
data = 0;
} else {
mask = data - 15;
}
} else {
mask = 7;
}
}
data = mask | (mask << 8);
ar7240_reg_wr(STEREO0_VOLUME, data);
return 0;
case I2S_FREQ:
data = arg;
switch (data) {
case 44100:
//ar7240_i2s_clk(0x0a47f028, 0x2383);
//cab = SPDIF_CONFIG_SAMP_FREQ(SPDIF_SAMP_FREQ_44);
//cab1 = SPDIF_CONFIG_ORG_FREQ(SPDIF_ORG_FREQ_44);
//ar7240_reg_wr(AR7240_STEREO_CLK_DIV,0xec330);//gl-inet
ar7240_reg_wr(AR7240_STEREO_CLK_DIV,((0x11 << 16) + 0xb6b0));//gl-inet 44100kHz
break;
case 48000:
//ar7240_i2s_clk(0x03c9f02c, 0x2383);
//cab = SPDIF_CONFIG_SAMP_FREQ(SPDIF_SAMP_FREQ_48);
//cab1 = SPDIF_CONFIG_ORG_FREQ(SPDIF_ORG_FREQ_48);
//ar7240_reg_wr(AR7240_STEREO_CLK_DIV,0xd9013);//gl-inet
ar7240_reg_wr(AR7240_STEREO_CLK_DIV,((0x10 << 16) + 0x4600));//gl-inet 48000kHz
break;
default:
printk(KERN_CRIT "Freq %d not supported \n",data);
return -ENOTSUPP;
}
for (j = 0; j < NUM_DESC; j++) {
dmabuf->db_desc[j].Ca[0] |= cab;
dmabuf->db_desc[j].Cb[0] |= cab;
dmabuf->db_desc[j].Ca[1] |= cab1;
dmabuf->db_desc[j].Cb[1] |= cab1;
}
return 0;
case I2S_FINE:
data = arg;
return 0;
case I2S_DSIZE:
data = arg;
switch (data) {
case 8:
st_cfg = (AR7240_STEREO_CONFIG_DEFAULT |
AR7240_STEREO_CONFIG_DATA_WORD_SIZE(AR7240_STEREO_WS_8B)
);
cab1 = SPDIF_CONFIG_SAMP_SIZE(SPDIF_S_8_16);
break;
case 16:
st_cfg = (AR7240_STEREO_CONFIG_DEFAULT |
AR7240_STEREO_CONFIG_PCM_SWAP |
AR7240_STEREO_CONFIG_DATA_WORD_SIZE(AR7240_STEREO_WS_16B)
);
cab1 = SPDIF_CONFIG_SAMP_SIZE(SPDIF_S_8_16);
break;
case 24:
st_cfg = (AR7240_STEREO_CONFIG_DEFAULT |
AR7240_STEREO_CONFIG_PCM_SWAP |
AR7240_STEREO_CONFIG_DATA_WORD_SIZE(AR7240_STEREO_WS_24B) |
AR7240_STEREO_CONFIG_I2S_32B_WORD
);
cab1 = SPDIF_CONFIG_SAMP_SIZE(SPDIF_S_24_32);
break;
case 32:
st_cfg = (AR7240_STEREO_CONFIG_DEFAULT |
AR7240_STEREO_CONFIG_PCM_SWAP |
AR7240_STEREO_CONFIG_DATA_WORD_SIZE(AR7240_STEREO_WS_32B) |
AR7240_STEREO_CONFIG_I2S_32B_WORD
);
cab1 = SPDIF_CONFIG_SAMP_SIZE(SPDIF_S_24_32);
break;
default:
printk(KERN_CRIT "Data size %d not supported \n",data);
return -ENOTSUPP;
}
ar7240_reg_wr(AR7240_STEREO_CONFIG, (st_cfg | AR7240_STEREO_CONFIG_RESET));
udelay(100);
ar7240_reg_rmw_clear(AR7240_STEREO_CONFIG,AR7240_STEREO_CONFIG_RESET);
ar7240_reg_wr(AR7240_STEREO_CONFIG, st_cfg);
for (j = 0; j < NUM_DESC; j++) {
dmabuf->db_desc[j].Ca[1] |= cab1;
dmabuf->db_desc[j].Cb[1] |= cab1;
}
return 0;
case I2S_MODE:
data = arg;
/* For MONO */
if (data != 2) {
ar7240_reg_rmw_set(AR7240_STEREO_CONFIG, MONO);
} else {
ar7240_reg_rmw_clear(AR7240_STEREO_CONFIG, MONO);
}
return 0;
case I2S_MCLK: /* Master clock is MCLK_IN or divided audio PLL */
data = arg;
if (data) {
ar7240_reg_wr(AUDIO_PLL, AUDIO_PLL_RESET); /* Reset Audio PLL */
ar7240_reg_rmw_set(AR7240_STEREO_CONFIG, AR7240_STEREO_CONFIG_I2S_MCLK_SEL);
} else {
ar7240_reg_rmw_clear(AR7240_STEREO_CONFIG, AR7240_STEREO_CONFIG_I2S_MCLK_SEL);
}
return 0;
case I2S_COUNT:
data = arg;
return 0;
default:
return -ETOOSMALL;
}
#endif
}
static int ag7240_check_link(ag7240_mac_t *mac)
{
u32 link, duplex, speed, fdx;
ag7240_phy_link(mac->mac_unit, &link);
ag7240_phy_duplex(mac->mac_unit, &duplex);
ag7240_phy_speed(mac->mac_unit, &speed);
mac->link = link;
#ifdef SUPPORT_PLC
if(strcmp(mac->dev->name, "eth0") == 0) {
printf("ag7240_check_link: %s link forced down\n",mac->dev->name);
return 0;
}
#endif
if(!mac->link) {
printf("%s link down\n",mac->dev->name);
return 0;
}
switch (speed)
{
case _1000BASET:
ag7240_set_mac_if(mac, 1);
ag7240_reg_rmw_set(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
if (is_ar7242() && (mac->mac_unit == 0)) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1c000000);
}
#ifdef CONFIG_F1E_PHY
if (is_wasp() && (mac->mac_unit == 0)) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x0e000000);
}
#elif CONFIG_VIR_PHY
if (is_wasp() && (mac->mac_unit == 0)) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x82000000);
ar7240_reg_wr(AG7240_ETH_CFG,0x000c0001);
}
#else
if (is_wasp() && (mac->mac_unit == 0) && !is_f2e()) {
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x06000000);
}
#endif
if (is_wasp() && mac->mac_unit == 0 && is_f1e() ) {
ar7240_reg_rmw_set(AG7240_ETH_CFG,AG7240_ETH_CFG_RXD_DELAY);
ar7240_reg_rmw_set(AG7240_ETH_CFG,AG7240_ETH_CFG_RDV_DELAY);
}
break;
case _100BASET:
ag7240_set_mac_if(mac, 0);
ag7240_set_mac_speed(mac, 1);
ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e())
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x0101);
if (is_wasp() && mac->mac_unit == 0 && is_f1e()) {
ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RXD_DELAY);
ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RDV_DELAY);
}
break;
case _10BASET:
ag7240_set_mac_if(mac, 0);
ag7240_set_mac_speed(mac, 0);
ag7240_reg_rmw_clear(mac, AG7240_MAC_FIFO_CFG_5, (1 << 19));
if ((is_ar7242() || is_wasp()) && (mac->mac_unit == 0) && !is_f2e())
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1616);
if (is_wasp() && mac->mac_unit == 0 && is_f1e()) {
ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RXD_DELAY);
ar7240_reg_rmw_clear(AG7240_ETH_CFG,AG7240_ETH_CFG_RDV_DELAY);
ar7240_reg_wr(AR7242_ETH_XMII_CONFIG,0x1313);
}
if (is_f2e()) {
ar7240_reg_rmw_clear(AG7240_ETH_CFG, AG7240_ETH_CFG_RMII_HISPD_GE0);
}
break;
default:
printf("Invalid speed detected\n");
return 0;
}
if (mac->link && (duplex == mac->duplex) && (speed == mac->speed))
return 1;
mac->duplex = duplex;
mac->speed = speed;
printf("dup %d speed %d\n", duplex, speed);
ag7240_set_mac_duplex(mac,duplex);
return 1;
}
int ag7240_enet_initialize(bd_t * bis) {
struct eth_device *dev[CFG_AG7240_NMACS];
u32 mask, mac_h, mac_l;
int i;
#ifdef AG7240_DEBUG
printf("ag7240_enet_initialize...\n");
#endif
// TODO check this register!
ar7240_reg_wr(HORNET_BOOTSTRAP_STATUS, ar7240_reg_rd(HORNET_BOOTSTRAP_STATUS) & ~HORNET_BOOTSTRAP_MDIO_SLAVE_MASK);
if (is_ar933x()) {
u32 rd = 0x0;
/*
* To get s26 out of reset, we have to...
* bit0~bit3: has to be deasserted
* bit4: has to be asserted
*/
rd = ar7240_reg_rd(AR7240_S26_CLK_CTRL_OFFSET) & ~(0x1f);
rd |= 0x10;
ar7240_reg_wr(AR7240_S26_CLK_CTRL_OFFSET, rd);
if (ar7240_reg_rd(AR7240_RESET) != 0) {
ar7240_reg_wr(AR7240_RESET, 0);
}
}
for (i = 0; i < CFG_AG7240_NMACS; i++) {
if ((dev[i] = (struct eth_device *) malloc(sizeof(struct eth_device))) == NULL) {
puts("## Error: malloc failed\n");
return 0;
}
if ((ag7240_macs[i] = (ag7240_mac_t *) malloc(sizeof(ag7240_mac_t))) == NULL) {
puts("## Error: malloc failed\n");
return 0;
}
memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
memset(dev[i], 0, sizeof(dev[i]));
sprintf(dev[i]->name, "eth%d", i);
ag7240_get_ethaddr(dev[i]);
ag7240_macs[i]->mac_unit = i;
ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE;
ag7240_macs[i]->dev = dev[i];
dev[i]->iobase = 0;
dev[i]->init = ag7240_clean_rx;
dev[i]->halt = ag7240_halt;
dev[i]->send = ag7240_send;
dev[i]->recv = ag7240_recv;
dev[i]->priv = (void *) ag7240_macs[i];
}
for (i = 0; i < CFG_AG7240_NMACS; i++) {
eth_register(dev[i]);
#if(CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);
#endif
ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST | AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);
if (!i) {
mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE0_PHY | AR7240_RESET_GE1_MAC | AR7240_RESET_GE1_PHY);
if (is_ar7241() || is_ar7242() || is_wasp()){
mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;
}
ar7240_reg_rmw_set(AR7240_RESET, mask);
if (!is_ar933x()){
udelay(1000 * 100);
}
ar7240_reg_rmw_clear(AR7240_RESET, mask);
if (!is_ar933x()){
udelay(1000 * 100);
}
if (!is_ar933x()){
udelay(10 * 1000);
}
}
ag7240_hw_start(ag7240_macs[i]);
ag7240_setup_fifos(ag7240_macs[i]);
if (!is_ar933x()){
udelay(100 * 1000);
}
#ifdef AG7240_DEBUG
unsigned char *mac = dev[i]->enetaddr;
printf("\nInterface %s MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n", dev[i]->name, mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff, mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
#endif
mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) | (dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);
/* if using header for register configuration, we have to */
/* configure s26 register after frame transmission is enabled */
if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */
#ifdef CONFIG_AR7242_S16_PHY
if (is_ar7242() || is_wasp()) {
athrs16_reg_init();
} else
#endif
{
#ifdef CFG_ATHRS26_PHY
#ifdef AG7240_DEBUG
printf("s26 reg init \n");
#endif
athrs26_reg_init();
#endif
#ifdef CFG_ATHRS27_PHY
#ifdef AG7240_DEBUG
printf("s27 reg init \n");
#endif
athrs27_reg_init();
#endif
#ifdef CONFIG_F1E_PHY
#ifdef AG7240_DEBUG
printf("F1Phy reg init \n");
#endif
athr_reg_init();
#endif
}
} else {
#ifdef CFG_ATHRS26_PHY
#ifdef AG7240_DEBUG
printf("athrs26_reg_init_lan\n");
#endif
athrs26_reg_init_lan();
#endif
#ifdef CFG_ATHRS27_PHY
#ifdef AG7240_DEBUG
printf("s27 reg init lan \n");
#endif
athrs27_reg_init_lan();
#endif
}
#ifdef AG7240_DEBUG
printf("ag7240_phy_setup\n");
#endif
//udelay(100*1000);
ag7240_phy_setup(ag7240_macs[i]->mac_unit);
#ifdef AG7240_DEBUG
printf("Interface %s is up\n", dev[i]->name);
#endif
}
return 1;
}
static void
ar7240_misc_irq_enable(unsigned int irq)
{
ar7240_reg_rmw_set(AR7240_MISC_INT_MASK,
(1 << (irq - AR7240_MISC_IRQ_BASE)));
}
void pci_init_board (void)
#endif /* #ifdef COMPRESSED_UBOOT */
{
#ifdef CONFIG_AP123
return;
#else
uint32_t cmd = 0, reg_val;
//printf("%s: PCIe PLL 0x%x\n", __func__, mips3_cp0_count_read());
//printf("%s: PCIe PLL 0x%x 0xb8000008 = 0x%08x\n", __func__, mips3_cp0_count_read(), ar7240_reg_rd(0xb8040008));
pci_udelay(100000);
//count ++;
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX,
PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0) |
PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(1) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x20) |
PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0));
} else {
#ifndef COMPRESSED_UBOOT
printf("%s: PCIe PLL not set for 40MHz refclk\n", __func__);
#endif
}
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE); // core in reset
pci_udelay(10000);
ar7240_reg_rmw_set(AR7240_RESET, AR7240_RESET_PCIE_PHY);// phy in reset
pci_udelay(10000);
ar7240_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog in reset
pci_udelay(10000);
ar7240_reg_wr(0x180f0000, 0x1ffc0); // ltssm is disabled
pci_udelay(100);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 0); // End point in reset
pci_udelay(100000);
//ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY);
if ((ar7240_reg_rd(AR7240_REV_ID) & 0xf) == 0) {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(1) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(0));
pci_udelay(1000);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
ar7240_reg_rd(AR934X_PCIE_PLL_CONFIG) &
(~PCIE_PLL_CONFIG_BYPASS_SET(1)));
pci_udelay(1000);
} else {
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG,
PCIE_PLL_CONFIG_REFDIV_SET(2) |
PCIE_PLL_CONFIG_BYPASS_SET(1) |
PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
ar7240_reg_wr_nf(0xb8116c00, (0x5 << 27) | (160 << 18) | 0);
} else {
ar7240_reg_wr_nf(0xb8116c00, (0x2 << 27) | (0x28 << 18) | 0);
}
do {
ar7240_reg_wr_nf(0xb8116c04, (0x1 << 30) | (0x4 << 26) | (0x32 << 19) | (1 << 16) | (3 << 13) | (0x1e << 7));
ar7240_reg_wr_nf(0xb8116c08, (6 << 23));
pci_udelay(10000);
ar7240_reg_wr_nf(0xb8116c04, (0x1 << 30) | (0x4 << 26) | (0x32 << 19) | (3 << 13) | (0x1e << 7));
ar7240_reg_rmw_clear(KSEG1ADDR(PCIe_DPLL3_ADDRESS), PCIe_DPLL3_DO_MEAS_SET(1));
ar7240_reg_rmw_set(KSEG1ADDR(PCIe_DPLL3_ADDRESS), PCIe_DPLL3_DO_MEAS_SET(1));
ar7240_reg_wr(0xb804000c, 1 << 2);
pci_udelay(1000);
while (((cmd = ar7240_reg_rd(PCIe_DPLL4_ADDRESS)) & PCIe_DPLL4_MEAS_DONE_SET(1)) == 0) {
printf("0x%x 0x%x 0x%x\n", KSEG1ADDR(PCIe_DPLL4_ADDRESS), cmd);
pci_udelay(10);
}
{ int i; for (i = 0; i < 100; i++) udelay(10); }
#if 0
msdvc = PCIe_DPLL4_MEAN_DVC_GET(cmd);
cmd = PCIe_DPLL3_SQSUM_DVC_GET(ar7240_reg_rd(PCIe_DPLL3_ADDRESS));
if (msdvc & 0x400) msdvc = ((~msdvc & 0x7FF) + 1); /* 11 bit signed number , but not intentioanlly multiply by (-1), ASK VIPUL*/
msdvc = cmd - (msdvc *msdvc);
msdvc_sq = msdvc * msdvc;
if (cmd >= 0x40000) {
err_count++;
if (sqsum_min_fail == 0)
sqsum_min_fail = cmd;
if (cmd > sqsum_max_fail)
sqsum_max_fail = cmd;
if (cmd < sqsum_min_fail)
sqsum_min_fail = cmd;
sqsum_avg_fail = (sqsum_avg_fail - (sqsum_avg_fail / err_count)) + (cmd / err_count);
if (num_pll_loops == 0)
err_pll1++;
if (num_pll_loops == 1)
err_pll2++;
if (num_pll_loops == 2)
err_pll3++;
if (num_pll_loops == 3)
err_pll4++;
if (num_pll_loops == 4) {
err_pll5++;
break;
}
} else {
if (sqsum_min == 0)
sqsum_min = cmd;
if (cmd < sqsum_min)
sqsum_min = cmd;
if (cmd > sqsum_max)
sqsum_max = cmd;
//sqsum_avg = (sqsum_avg - (sqsum_avg / count)) + (cmd / count);
sqsum_avg += cmd;
/*msdvc calc*/
if (msdvc_min == 0) msdvc_min = msdvc;
if (msdvc < msdvc_min) msdvc_min =msdvc;
if (msdvc > msdvc_max) msdvc_max =msdvc;
msdvc_avg += msdvc;
msdvc_sq_avg += msdvc_sq;
}
num_pll_loops++;
#endif
} while ((cmd = PCIe_DPLL3_SQSUM_DVC_GET(ar7240_reg_rd(PCIe_DPLL3_ADDRESS))) >= 0x40000);
ar7240_reg_rmw_clear(AR934X_PCIE_PLL_CONFIG, PCIE_PLL_CONFIG_PLLPWD_SET(1));
pci_udelay(10000);
ar7240_reg_rmw_clear(AR934X_PCIE_PLL_CONFIG, PCIE_PLL_CONFIG_BYPASS_SET(1));
pci_udelay(10000);
/*
* PCIe Dithering configuration
*/
if (is_ar934x_12_or_later()) {
ar7240_reg_wr_nf(PCIe_DPLL2_ADDRESS,
PCIe_DPLL2_LOCAL_PLL_SET(0) |
PCIe_DPLL2_KI_SET(0x4)|
PCIe_DPLL2_KD_SET(0x40));
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x40010800);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MAX, 0xc013fffe);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_DITHER_DIV_MIN, 0x0013e666);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x00010800);
ar7240_reg_wr_nf(AR934X_PCIE_PLL_CONFIG, 0x00000800);
}
//run_command("md 0xb8116c00 4", 0);
}
ar7240_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); // pci phy analog out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE_PHY); // phy out of reset
pci_udelay(10000);
ar7240_reg_rmw_clear(AR7240_RESET, AR7240_RESET_PCIE); // core out of reset
pci_udelay(1000);
cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
ar7240_local_write_config(PCI_COMMAND, 4, cmd); // pci cmd reg init
ar7240_local_write_config(0x20, 4, 0x1ff01000); // membase setting
ar7240_local_write_config(0x24, 4, 0x1ff01000); // prefetch membase setting
if ((is_ar7241() || is_ar7242() || is_wasp())) {
ar7240_reg_wr(0x180f0000, 0x1ffc1); // ltssm enable
} else {
ar7240_reg_wr(0x180f0000, 0x1);
}
pci_udelay(100000);
ar7240_reg_wr_nf(AR7240_PCI_LCL_RESET, 4); // EP out of reset
pci_udelay(100000);
#ifdef COMPRESSED_UBOOT
pci_udelay(100);
#else
/*
* Delay increased from 100 to 1000, so as to
* get the correct status from PCI LCL RESET register
*/
pci_udelay(100000);
/*
* Check if the WLAN PCI-E H/W is present, If the
* WLAN H/W is not present, skip the PCI platform
* initialization code and return
*/
if (((ar7240_reg_rd(AR7240_PCI_LCL_RESET)) & 0x1) == 0x0) {
printf("*** Warning *** : PCIe WLAN Module not found !!!\n");
return;
}
#endif
#ifndef COMPRESSED_UBOOT
/*
* Now, configure for u-boot tools
*/
hose.first_busno = 0;
hose.last_busno = 0xff;
/* System space */
pci_set_region( &hose.regions[0],
0x80000000,
0x00000000,
32 * 1024 * 1024,
PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region( &hose.regions[1],
0x10000000,
0x10000000,
128 * 1024 * 1024,
PCI_REGION_MEM);
hose.region_count = 2;
pci_register_hose(&hose);
pci_set_ops( &hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
ar7240_pci_read_config,
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
ar7240_pci_write_config);
#endif
plat_dev_init();
#endif // CONFIG_AP123
#ifdef COMPRESSED_UBOOT
return 0;
#endif
}
/*
* Called in ag7240_hw_start() function
* */
void ag7240_mii_setup(ag7240_mac_t *mac) {
u32 mgmt_cfg_val;
u32 cpu_freq, ddr_freq, ahb_freq;
u32 check_cnt;
#ifdef CFG_ATHRS27_PHY
if (is_wasp()) {
printf("WASP ----> S27 PHY \n");
mgmt_cfg_val = 2;
ar7240_reg_wr(0xb8050024, 0x271); // 25MHz ref clock
//ar7240_reg_wr(0xb8050024, 0x570); // 40MHz ref clock
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#ifdef CONFIG_AR7242_S16_PHY
if (is_wasp()) {
printf("WASP ----> S16 PHY *\n");
mgmt_cfg_val = 4;
if(mac->mac_unit == 0)
ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
ar7240_reg_rmw_clear(AG7240_ETH_SWITCH_CLK_SPARE, (1 << 6));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#ifdef CONFIG_F1E_PHY
if (is_wasp()) {
printf("WASP ----> F1 PHY *\n");
mgmt_cfg_val = 6;
if(mac->mac_unit == 0)
ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
if ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) {
mgmt_cfg_val = 0x2;
if (mac->mac_unit == 0) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
} else {
ar933x_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
switch (ahb_freq / 1000000) {
case 150:
mgmt_cfg_val = 0x7;
break;
case 175:
mgmt_cfg_val = 0x5;
break;
case 200:
mgmt_cfg_val = 0x4;
break;
case 210:
mgmt_cfg_val = 0x9;
break;
case 220:
mgmt_cfg_val = 0x9;
break;
default:
mgmt_cfg_val = 0x7;
}
if ((is_ar7241() || is_ar7242())) {
/* External MII mode */
if (mac->mac_unit == 0 && is_ar7242()) {
mgmt_cfg_val = 0x6;
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
/* Virian */
mgmt_cfg_val = 0x4;
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
printf("Virian MDC CFG Value ==> %x\n", mgmt_cfg_val);
} else if (is_ar933x()) {
//GE0 receives Rx/Tx clock, and use S26 phy
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE);
mgmt_cfg_val = 0xF;
if (mac->mac_unit == 1) {
check_cnt = 0;
while (check_cnt++ < 10) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
if (athrs26_mdc_check() == 0) {
break;
}
#endif
}
if (check_cnt == 11) {
printf("%s: MDC check failed\n", __func__);
}
}
} else { /* Python 1.0 & 1.1 */
if (mac->mac_unit == 0) {
check_cnt = 0;
while (check_cnt++ < 10) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
if (athrs26_mdc_check() == 0) {
break;
}
#endif
}
if (check_cnt == 11) {
printf("%s: MDC check failed\n", __func__);
}
}
}
}
}
void
ar7240_gpio_config_output(int gpio)
{
ar7240_reg_rmw_set(AR7240_GPIO_OE, (1 << gpio));
}
void ag7240_mii_setup(ag7240_mac_t *mac)
{
u32 mgmt_cfg_val;
u32 cpu_freq,ddr_freq,ahb_freq;
u32 check_cnt,revid_val;
if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0) {
#ifndef CFG_DUAL_PHY_SUPPORT
ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x271);
#endif
} else {
ar7240_reg_wr(AR934X_SWITCH_CLOCK_SPARE, 0x570);
}
#if defined(CONFIG_AR7242_S16_PHY) || defined(CONFIG_ATHRS17_PHY)
if (is_wasp() && mac->mac_unit == 0) {
#ifdef CONFIG_AR7242_S16_PHY
printf("WASP ----> S16 PHY *\n");
#else
printf("WASP ----> S17 PHY *\n");
#endif
mgmt_cfg_val = 4;
if(mac->mac_unit == 0)
ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
udelay(1000);
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#ifdef CFG_ATHRS27_PHY
if (is_wasp()) {
printf("WASP ----> S27 PHY \n");
mgmt_cfg_val = 2;
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#ifdef CONFIG_F2E_PHY
if (is_wasp()) {
printf("WASP ----> F2 PHY *\n");
ar7240_reg_wr(AG7240_ETH_CFG, (AG7240_ETH_CFG_RMII_MASTER_MODE | AG7240_ETH_CFG_RMII_GE0
| AG7240_ETH_CFG_RMII_HISPD_GE0));
mgmt_cfg_val = 6;
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
#if defined(CONFIG_F1E_PHY) || defined(CONFIG_VIR_PHY)
if (is_wasp()) {
#ifdef CONFIG_VIR_PHY
printf("WASP ----> VIR PHY *\n");
#else
printf("WASP ----> F1 PHY *\n");
#endif
if(mac->mac_unit == 0)
ar7240_reg_wr(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
mgmt_cfg_val = 6;
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
return;
}
#endif
if ((ar7240_reg_rd(AR7240_REV_ID) & AR7240_REV_ID_MASK) == AR7240_REV_1_2) {
mgmt_cfg_val = 0x2;
if (mac->mac_unit == 0) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
}
else {
ar7240_sys_frequency(&cpu_freq, &ddr_freq, &ahb_freq);
switch (ahb_freq/1000000) {
case 150:
mgmt_cfg_val = 0x7;
break;
case 175:
mgmt_cfg_val = 0x5;
break;
case 200:
mgmt_cfg_val = 0x4;
break;
case 210:
mgmt_cfg_val = 0x9;
break;
case 220:
mgmt_cfg_val = 0x9;
break;
default:
mgmt_cfg_val = 0x7;
}
if ((is_ar7241() || is_ar7242())) {
/* External MII mode */
if (mac->mac_unit == 0 && is_ar7242()) {
mgmt_cfg_val = 0x6;
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_RGMII_GE0);
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
}
/* Virian */
mgmt_cfg_val = 0x4;
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(ag7240_macs[1], AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
printf("Virian MDC CFG Value ==> %x\n",mgmt_cfg_val);
}
else if(is_ar933x()) {
//GE0 receives Rx/Tx clock, and use S26 phy
ar7240_reg_rmw_set(AG7240_ETH_CFG, AG7240_ETH_CFG_MII_GE0_SLAVE);
mgmt_cfg_val = 0xF;
if (mac->mac_unit == 1) {
check_cnt = 0;
while (check_cnt++ < 10) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
if(athrs26_mdc_check() == 0)
break;
#endif
}
if(check_cnt == 11)
printf("%s: MDC check failed\n", __func__);
}
}
else { /* Python 1.0 & 1.1 */
if (mac->mac_unit == 0) {
check_cnt = 0;
while (check_cnt++ < 10) {
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val | (1 << 31));
ag7240_reg_wr(mac, AG7240_MAC_MII_MGMT_CFG, mgmt_cfg_val);
#ifdef CFG_ATHRS26_PHY
if(athrs26_mdc_check() == 0)
break;
#endif
}
if(check_cnt == 11)
printf("%s: MDC check failed\n", __func__);
}
}
}
}
static void
ar7240_gpio_intr_enable(unsigned int irq)
{
ar7240_reg_rmw_set(AR7240_GPIO_INT_MASK,
(1 << (irq - AR7240_GPIO_IRQ_BASE)));
}
static void ag7240_get_ethaddr(struct eth_device *dev)
{
unsigned char *eeprom;
unsigned char *mac = dev->enetaddr;
#ifndef CONFIG_AR7240_EMU
#ifdef CONFIG_ATH_NAND_BR
unsigned char sectorBuff[ATH_ETH_MAC_READ_SIZE];
eeprom = ath_eth_mac_addr(sectorBuff);
if(eeprom == NULL) {
/* mac address will be set to default mac address */
mac[0] = 0xff;
}
else {
#else /* CONFIG_ATH_NAND_BR */
eeprom = ag7240_mac_addr_loc();
#endif /* CONFIG_ATH_NAND_BR */
if (strcmp(dev->name, "eth0") == 0) {
memcpy(mac, eeprom, 6);
} else if (strcmp(dev->name, "eth1") == 0) {
eeprom += 6;
memcpy(mac, eeprom, 6);
} else {
printf("%s: unknown ethernet device %s\n", __func__, dev->name);
return;
}
#ifdef CONFIG_ATH_NAND_BR
}
#endif /* CONFIG_ATH_NAND_BR */
/* Use fixed address if the above address is invalid */
if (mac[0] != 0x00 || (mac[0] == 0xff && mac[5] == 0xff)) {
#else
if (1) {
#endif
mac[0] = 0x00;
mac[1] = 0x03;
mac[2] = 0x7f;
mac[3] = 0x09;
mac[4] = 0x0b;
mac[5] = 0xad;
printf("No valid address in Flash. Using fixed address\n");
} else {
printf("Fetching MAC Address from 0x%p\n", __func__, eeprom);
}
}
int ag7240_enet_initialize(bd_t * bis)
{
struct eth_device *dev[CFG_AG7240_NMACS];
u32 mask, mac_h, mac_l;
int i;
printf("ag934x_enet_initialize...\n");
if(is_ar933x() && (ar7240_reg_rd(AR7240_RESET)!=0))
ar7240_reg_wr(AR7240_RESET,0);
if(is_ar933x()) //Turn on LED
ar7240_reg_wr(AR7240_GPIO_BASE + 0x28 , ar7240_reg_rd(AR7240_GPIO_BASE + 0x28) | (0xF8));
for (i = 0; i < CFG_AG7240_NMACS; i++) {
if ((dev[i] = (struct eth_device *) malloc(sizeof (struct eth_device))) == NULL) {
puts("malloc failed\n");
return 0;
}
if ((ag7240_macs[i] = (ag7240_mac_t *) malloc(sizeof (ag7240_mac_t))) == NULL) {
puts("malloc failed\n");
return 0;
}
memset(ag7240_macs[i], 0, sizeof(ag7240_macs[i]));
memset(dev[i], 0, sizeof(dev[i]));
sprintf(dev[i]->name, "eth%d", i);
ag7240_get_ethaddr(dev[i]);
ag7240_macs[i]->mac_unit = i;
ag7240_macs[i]->mac_base = i ? AR7240_GE1_BASE : AR7240_GE0_BASE ;
ag7240_macs[i]->dev = dev[i];
dev[i]->iobase = 0;
dev[i]->init = ag7240_clean_rx;
dev[i]->halt = ag7240_halt;
dev[i]->send = ag7240_send;
dev[i]->recv = ag7240_recv;
dev[i]->priv = (void *)ag7240_macs[i];
}
#if !defined(CONFIG_ATH_NAND_BR)
mask = AR7240_RESET_GE1_PHY;
ar7240_reg_rmw_set(AR7240_RESET, mask);
udelay(1000 * 100);
ar7240_reg_rmw_clear(AR7240_RESET, mask);
udelay(100);
#endif
mask = AR7240_RESET_GE0_PHY;
ar7240_reg_rmw_set(AR7240_RESET, mask);
udelay(1000 * 100);
ar7240_reg_rmw_clear(AR7240_RESET, mask);
udelay(100);
for (i = 0; i < CFG_AG7240_NMACS; i++) {
eth_register(dev[i]);
#if(CONFIG_COMMANDS & CFG_CMD_MII)
miiphy_register(dev[i]->name, ag7240_miiphy_read, ag7240_miiphy_write);
#endif
ag7240_reg_rmw_set(ag7240_macs[i], AG7240_MAC_CFG1, AG7240_MAC_CFG1_SOFT_RST
| AG7240_MAC_CFG1_RX_RST | AG7240_MAC_CFG1_TX_RST);
if(!i) {
mask = (AR7240_RESET_GE0_MAC | AR7240_RESET_GE1_MAC);
if (is_ar7241() || is_ar7242() || is_wasp())
mask = mask | AR7240_RESET_GE0_MDIO | AR7240_RESET_GE1_MDIO;
printf(" wasp reset mask:%x \n",mask);
ar7240_reg_rmw_set(AR7240_RESET, mask);
udelay(1000 * 100);
ar7240_reg_rmw_clear(AR7240_RESET, mask);
udelay(1000 * 100);
udelay(10 * 1000);
}
ag7240_mii_setup(ag7240_macs[i]);
/* if using header for register configuration, we have to */
/* configure s26 register after frame transmission is enabled */
if (ag7240_macs[i]->mac_unit == 0) { /* WAN Phy */
#ifdef CONFIG_AR7242_S16_PHY
if (is_ar7242() || is_wasp()) {
athrs16_reg_init();
} else
#endif
{
#ifdef CONFIG_ATHRS17_PHY
athrs17_reg_init();
#endif
#ifdef CFG_ATHRS26_PHY
athrs26_reg_init();
#endif
#ifdef CFG_ATHRS27_PHY
printf("s27 reg init \n");
athrs27_reg_init();
#endif
#ifdef CONFIG_F1E_PHY
printf("F1Phy reg init \n");
athr_reg_init();
#endif
#ifdef CONFIG_VIR_PHY
printf("VIRPhy reg init \n");
athr_vir_reg_init();
#endif
#ifdef CONFIG_F2E_PHY
printf("F2Phy reg init \n");
athr_reg_init();
#endif
}
} else {
#ifdef CFG_ATHRS26_PHY
athrs26_reg_init_lan();
#endif
#ifdef CFG_ATHRS27_PHY
printf("s27 reg init lan \n");
athrs27_reg_init_lan();
#endif
}
ag7240_hw_start(ag7240_macs[i]);
ag7240_setup_fifos(ag7240_macs[i]);
udelay(100 * 1000);
{
unsigned char *mac = dev[i]->enetaddr;
printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev[i]->name,
mac[0] & 0xff, mac[1] & 0xff, mac[2] & 0xff,
mac[3] & 0xff, mac[4] & 0xff, mac[5] & 0xff);
}
mac_l = (dev[i]->enetaddr[4] << 8) | (dev[i]->enetaddr[5]);
mac_h = (dev[i]->enetaddr[0] << 24) | (dev[i]->enetaddr[1] << 16) |
(dev[i]->enetaddr[2] << 8) | (dev[i]->enetaddr[3] << 0);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR1, mac_l);
ag7240_reg_wr(ag7240_macs[i], AG7240_GE_MAC_ADDR2, mac_h);
ag7240_phy_setup(ag7240_macs[i]->mac_unit);
printf("%s up\n",dev[i]->name);
}
return 1;
}
#if (CONFIG_COMMANDS & CFG_CMD_MII)
int
ag7240_miiphy_read(char *devname, uint32_t phy_addr, uint8_t reg, uint16_t *data)
{
ag7240_mac_t *mac = ag7240_name2mac(devname);
uint16_t addr = (phy_addr << AG7240_ADDR_SHIFT) | reg, val;
volatile int rddata;
uint16_t ii = 0xFFFF;
/*
* Check for previous transactions are complete. Added to avoid
* race condition while running at higher frequencies.
*/
do
{
udelay(5);
rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
} while(rddata && --ii);
if (ii == 0)
printf("ERROR:%s:%d transaction failed\n",__func__,__LINE__);
ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);
ag7240_reg_wr(mac, AG7240_MII_MGMT_ADDRESS, addr);
ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, AG7240_MGMT_CMD_READ);
do
{
udelay(5);
rddata = ag7240_reg_rd(mac, AG7240_MII_MGMT_IND) & 0x1;
} while(rddata && --ii);
if(ii==0)
printf("Error!!! Leave ag7240_miiphy_read without polling correct status!\n");
val = ag7240_reg_rd(mac, AG7240_MII_MGMT_STATUS);
ag7240_reg_wr(mac, AG7240_MII_MGMT_CMD, 0x0);
if(data != NULL)
*data = val;
return val;
}
void ar7240_i2sound_i2slink_on(int master)
{
/* Clear all resets */
ar7240_reg_wr(RST_RESET, 0);
udelay(500);
/*Set GPIO control wm8978 */
//ar7240_reg_wr(AR7240_GPIO_OE,(AR7240_LED_3|AR7240_LED_4|AR7240_LED_5));
ar7240_reg_wr(AR7240_GPIO_OE,(IIS_CONTROL_CSB|IIS_CONTROL_SDIN|IIS_CONTROL_SCLK));
/* Set GPIO I2S Enables */
/*
* 0x3c000001 should be set to GPIO for MIC and I2S
* 0x7c000001 should be set to GPIO for SPDIF
*
*AR7240_GPIO_FUNCTION_SPDIF_EN:Enables GPIO_23 or TCK as the SPDIF serial output
*AR7240_GPIO_FUNCTION_I2S_MCKEN:Enables the master audio CLK_MCK to be output through GPIO_21. \
*Works only if I2S0_22_18_EN (bit [29]) is also set
*AR7240_GPIO_FUNCTION_I2S0_EN:Enables I2S functions on GPIO pins
*/
ar7240_reg_rmw_set(AR7240_GPIO_FUNCTIONS,
(AR7240_GPIO_FUNCTION_SPDIF_EN |
AR7240_GPIO_FUNCTION_I2S_MCKEN |
AR7240_GPIO_FUNCTION_I2S0_EN|
AR7240_GPIO_FUNCTION_I2S_GPIO_18_22_EN
));
#if 0
/*
* GPIO 13 and GPIO 14 are used for I2S logic.
* So disabling LED on these pins.
*/
ar7240_reg_rmw_clear(AR7240_GPIO_FUNCTIONS,
(AR7240_GPIO_FUNCTION_ETH_SWITCH_LED1_EN |
AR7240_GPIO_FUNCTION_ETH_SWITCH_LED0_EN
));
//AR7240_GPIO_FUNCTION_2_EN_I2WS_ON_0 :Enables I2S_WS on GPIO_0
//AR7240_GPIO_FUNCTION_2_EN_I2SCK_ON_1:Enables I2S_CK Out on GPIO_1
//AR7240_GPIO_FUNCTION_2_I2S_ON_LED :Brings out I2S related signals on pins GPIO_14, GPIO_15 and GPIO_16
ar7240_reg_rmw_set(AR7240_GPIO_FUNCTION_2,
(AR7240_GPIO_FUNCTION_2_EN_I2WS_ON_0 |
AR7240_GPIO_FUNCTION_2_EN_I2SCK_ON_1 |
AR7240_GPIO_FUNCTION_2_I2S_ON_LED));
#endif
/* AR7240_STEREO_CONFIG should carry 0x201302 for MIC and I2S
* AR7240_STEREO_CONFIG should carry 0xa01302 for SPDIF
*/
//AR7240_STEREO_CONFIG_PCM_SWAP:This bit is used for swapping byte order of PCM samples
//AR7240_STEREO_CONFIG_SPDIF_ENABLE:Enables the SPDIF stereo block for operation
//AR7240_STEREO_CONFIG_RESET:Resets the stereo buffers and I2S state; Should be written to 1 when any of
//the data word sizes change, or if data synchronization is lost. Hardware will
//automatically clear to 0 //AR7240_STEREO_CONFIG_ENABLE:Enables operation of the I2S stereo block
//AR7240_STEREO_CONFIG_DATA_WORD_SIZE(AR7240_STEREO_WS_16B):
//Controls the word size loaded into the PCM register from the MBOX FIFO.
//Data word size:
//0x0 8 bits/word
//0x1 16 bits/word
//0x2 24 bits/word
//0x3 32 bits/word
//AR7240_STEREO_CONFIG_SAMPLE_CNT_CLEAR_TYPE:see datasheet
//AR7240_STEREO_CONFIG_MASTER:The AR9331 is the master and drives I2S_CK and I2S_WS
//AR7240_STEREO_CONFIG_PSEDGE(2):see datasheet //
ar7240_reg_wr(AR7240_STEREO_CONFIG,
(AR7240_STEREO_CONFIG_SPDIF_ENABLE|
AR7240_STEREO_CONFIG_ENABLE|
AR7240_STEREO_CONFIG_RESET|
AR7240_STEREO_CONFIG_PCM_SWAP|
AR7240_STEREO_CONFIG_MIC_WORD_SIZE|
AR7240_STEREO_CONFIG_MODE(0)|
AR7240_STEREO_CONFIG_DATA_WORD_SIZE(AR7240_STEREO_WS_16B)|
AR7240_STEREO_CONFIG_I2S_32B_WORD|
AR7240_STEREO_CONFIG_SAMPLE_CNT_CLEAR_TYPE|
AR7240_STEREO_CONFIG_MASTER|
AR7240_STEREO_CONFIG_PSEDGE(2)
));//gl-inet
//ar7240_reg_wr(AR7240_STEREO_CLK_DIV,0xec330);//gl-inet
//ar7240_reg_wr(AR7240_STEREO_CLK_DIV,0xd9013);//gl-inet
//ar7240_reg_wr(AR7240_STEREO_CLK_DIV,((0x10 << 16) + 0x4600));//gl-inet 48000kHz
ar7240_reg_wr(AR7240_STEREO_CLK_DIV,((0x11 << 16) + 0xb6b0));//gl-inet 44100kHz
init_wm8978();
#if 0
{
ar7240_gpio_setpin(AR7240_LED_8,1);
mdelay(200);
ar7240_gpio_setpin(AR7240_LED_4,1);
mdelay(200);
ar7240_gpio_setpin(AR7240_LED_5,1);
mdelay(200);
//mdelay(500);
ar7240_gpio_setpin(AR7240_LED_8,0);
mdelay(200);
ar7240_gpio_setpin(AR7240_LED_4,0);
mdelay(200);
ar7240_gpio_setpin(AR7240_LED_5,0);
mdelay(200);
ar7240_gpio_setpin(AR7240_LED_8,1);
mdelay(200);
ar7240_gpio_setpin(AR7240_LED_4,1);
mdelay(200);
ar7240_gpio_setpin(AR7240_LED_5,1);
mdelay(200);
ar7240_gpio_setpin(AR7240_LED_8,0);
mdelay(200);
ar7240_gpio_setpin(AR7240_LED_4,0);
mdelay(200);
ar7240_gpio_setpin(AR7240_LED_5,0);
mdelay(200);
//mdelay(500);
}
#endif
udelay(100);
ar7240_reg_rmw_clear(AR7240_STEREO_CONFIG, AR7240_STEREO_CONFIG_RESET);
}
