int arc_ocd_examine(struct target *target)
{
	uint32_t status;
	struct arc32_common *arc32 = target_to_arc32(target);

	LOG_DEBUG("-");
	CHECK_RETVAL(arc_jtag_startup(&arc32->jtag_info));

	if (!target_was_examined(target)) {
		CHECK_RETVAL(arc_jtag_status(&arc32->jtag_info, &status));
		if (status & ARC_JTAG_STAT_RU) {
			target->state = TARGET_RUNNING;
		} else {
			/* It is first time we examine the target, it is halted
			 * and we don't know why. Let's set debug reason,
			 * otherwise OpenOCD will complain that reason is
			 * unknown. */
			if (target->state == TARGET_UNKNOWN)
				target->debug_reason = DBG_REASON_DBGRQ;
			target->state = TARGET_HALTED;
		}

		/* Read BCRs and configure optional registers. */
		CHECK_RETVAL(arc32_configure(target));

		target_set_examined(target);
	}

	return ERROR_OK;
}
示例#2
0
int arc_ocd_examine(struct target *target)
{
	uint32_t status;
	struct arc32_common *arc32 = target_to_arc32(target);

	LOG_DEBUG("-");
	CHECK_RETVAL(arc_jtag_startup(&arc32->jtag_info));

	if (!target_was_examined(target)) {
		/* read ARC core info */
		if (strncmp(target_name(target), ARCEM_STR, 6) == 0) {
			arc32->processor_type = ARCEM_NUM;
			LOG_USER("Processor type: %s", ARCEM_STR);

		} else if (strncmp(target_name(target), ARC600_STR, 6) == 0) {
			arc32->processor_type = ARC600_NUM;
			LOG_USER("Processor type: %s", ARC600_STR);

		} else if (strncmp(target_name(target), ARC700_STR, 6) == 0) {
			arc32->processor_type = ARC700_NUM;
			LOG_USER("Processor type: %s", ARC700_STR);

		} else {
			LOG_WARNING(" THIS IS A UNSUPPORTED TARGET: %s", target_name(target));
		}

		CHECK_RETVAL(arc_jtag_status(&arc32->jtag_info, &status));
		if (status & ARC_JTAG_STAT_RU) {
			target->state = TARGET_RUNNING;
		} else {
			/* It is first time we examine the target, it is halted
			 * and we don't know why. Let's set debug reason,
			 * otherwise OpenOCD will complain that reason is
			 * unknown. */
			if (target->state == TARGET_UNKNOWN)
				target->debug_reason = DBG_REASON_DBGRQ;
			target->state = TARGET_HALTED;
		}

		/* Read BCRs and configure optinal registers. */
		CHECK_RETVAL(arc_regs_read_bcrs(target));
		arc_regs_build_reg_list(target);
		CHECK_RETVAL(arc32_configure(target));

		target_set_examined(target);
	}

	return ERROR_OK;
}