int sunxi_arisc_wait_ready(void)
{
ARISC_INF("wait arisc ready....\n");
if (arisc_wait_ready(10000)) {
ARISC_LOG("arisc startup failed\n");
}
arisc_set_paras();
ARISC_LOG("sunxi-arisc driver v%s startup ok\n", DRV_VERSION);
return 0;
}
int sunxi_arisc_probe(void *cfg)
{
struct arisc_para para;
ARISC_LOG("sunxi-arisc driver begin startup %d\n", arisc_debug_level);
memcpy((void *)&dts_cfg, (const void *)cfg, sizeof(struct dts_cfg));
/* init arisc parameter */
sunxi_arisc_para_init(¶);
/* load arisc */
sunxi_load_arisc(dts_cfg.image.base, dts_cfg.image.size,
(void *)(¶), sizeof(struct arisc_para));
/* initialize hwspinlock */
ARISC_INF("hwspinlock initialize\n");
arisc_hwspinlock_init();
/* initialize hwmsgbox */
ARISC_INF("hwmsgbox initialize\n");
arisc_hwmsgbox_init();
/* initialize message manager */
ARISC_INF("message manager initialize start:0x%llx, size:0x%llx\n", dts_cfg.space.msgpool_dst, dts_cfg.space.msgpool_size);
arisc_message_manager_init((void *)dts_cfg.space.msgpool_dst, dts_cfg.space.msgpool_size);
/* wait arisc ready */
ARISC_INF("wait arisc ready....\n");
if (arisc_wait_ready(10000)) {
ARISC_LOG("arisc startup failed\n");
}
arisc_set_paras();
/* enable arisc asyn tx interrupt */
//arisc_hwmsgbox_enable_receiver_int(ARISC_HWMSGBOX_ARISC_ASYN_TX_CH, AW_HWMSG_QUEUE_USER_AC327);
/* enable arisc syn tx interrupt */
//arisc_hwmsgbox_enable_receiver_int(ARISC_HWMSGBOX_ARISC_SYN_TX_CH, AW_HWMSG_QUEUE_USER_AC327);
/* arisc initialize succeeded */
ARISC_LOG("sunxi-arisc driver v%s is starting\n", DRV_VERSION);
return 0;
}
static int sunxi_arisc_probe(struct platform_device *pdev)
{
int binary_len;
int ret;
ARISC_INF("arisc initialize\n");
/* cfg sunxi arisc clk */
ret = sunxi_arisc_clk_cfg(pdev);
if (ret) {
ARISC_ERR("sunxi-arisc clk cfg failed\n");
return -EINVAL;
}
/* cfg sunxi arisc pin */
ret = sunxi_arisc_pin_cfg(pdev);
if (ret) {
ARISC_ERR("sunxi-arisc pin cfg failed\n");
return -EINVAL;
}
ARISC_INF("sram_a2 vaddr(%x)\n", (unsigned int)arisc_sram_a2_vbase);
#if (defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN8IW3P1) || (defined CONFIG_ARCH_SUN8IW5P1) || (defined CONFIG_ARCH_SUN8IW6P1)
binary_len = 0x13000;
#elif defined CONFIG_ARCH_SUN9IW1P1
binary_len = (int)(&arisc_binary_end) - (int)(&arisc_binary_start);
#endif
/* clear sram_a2 area */
memset((void *)arisc_sram_a2_vbase, 0, SUNXI_SRAM_A2_SIZE);
/* load arisc system binary data to sram_a2 */
memcpy((void *)arisc_sram_a2_vbase, (void *)(&arisc_binary_start), binary_len);
ARISC_INF("move arisc binary data [addr = %x, len = %x] to sram_a2 finished\n",
(unsigned int)(&arisc_binary_start), (unsigned int)binary_len);
/* initialize hwspinlock */
ARISC_INF("hwspinlock initialize\n");
arisc_hwspinlock_init();
/* initialize hwmsgbox */
ARISC_INF("hwmsgbox initialize\n");
arisc_hwmsgbox_init();
/* initialize message manager */
ARISC_INF("message manager initialize\n");
arisc_message_manager_init();
/* set arisc cpu reset to de-assert state */
ARISC_INF("set arisc reset to de-assert state\n");
#if (defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN8IW3P1) || (defined CONFIG_ARCH_SUN8IW5P1) || (defined CONFIG_ARCH_SUN8IW6P1)
{
volatile unsigned long value;
value = readl((IO_ADDRESS(SUNXI_R_CPUCFG_PBASE) + 0x0));
value &= ~1;
writel(value, (IO_ADDRESS(SUNXI_R_CPUCFG_PBASE) + 0x0));
value = readl((IO_ADDRESS(SUNXI_R_CPUCFG_PBASE) + 0x0));
value |= 1;
writel(value, (IO_ADDRESS(SUNXI_R_CPUCFG_PBASE) + 0x0));
}
#elif defined CONFIG_ARCH_SUN9IW1P1
{
volatile unsigned long value;
value = readl((IO_ADDRESS(SUNXI_R_PRCM_PBASE) + 0x0));
value &= ~1;
writel(value, (IO_ADDRESS(SUNXI_R_PRCM_PBASE) + 0x0));
value = readl((IO_ADDRESS(SUNXI_R_PRCM_PBASE) + 0x0));
value |= 1;
writel(value, (IO_ADDRESS(SUNXI_R_PRCM_PBASE) + 0x0));
}
#endif
/* wait arisc ready */
ARISC_INF("wait arisc ready....\n");
if (arisc_wait_ready(10000)) {
ARISC_LOG("arisc startup failed\n");
}
/* enable arisc asyn tx interrupt */
arisc_hwmsgbox_enable_receiver_int(ARISC_HWMSGBOX_ARISC_ASYN_TX_CH, AW_HWMSG_QUEUE_USER_AC327);
/* enable arisc syn tx interrupt */
arisc_hwmsgbox_enable_receiver_int(ARISC_HWMSGBOX_ARISC_SYN_TX_CH, AW_HWMSG_QUEUE_USER_AC327);
/* config dvfs v-f table */
if (arisc_dvfs_cfg_vf_table()) {
ARISC_WRN("config dvfs v-f table failed\n");
}
#if (defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN8IW6P1) || (defined CONFIG_ARCH_SUN9IW1P1)
/* config ir config paras */
if (arisc_config_ir_paras()) {
ARISC_WRN("config ir paras failed\n");
}
#endif
#if (defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN8IW3P1) || (defined CONFIG_ARCH_SUN8IW5P1)
/* config pmu config paras */
if (arisc_config_pmu_paras()) {
ARISC_WRN("config pmu paras failed\n");
}
#endif
/* config dram config paras */
if (arisc_config_dram_paras()) {
ARISC_WRN("config dram paras failed\n");
}
#if (defined CONFIG_ARCH_SUN8IW5P1) || (defined CONFIG_ARCH_SUN9IW1P1)
/* config standby power paras */
if (arisc_sysconfig_sstpower_paras()) {
ARISC_WRN("config sst power paras failed\n");
}
#endif
atomic_set(&arisc_suspend_flag, 0);
/*
* detect sunxi chip id
* include soc chip id, pmu chip id and serial.
*/
sunxi_chip_id_init();
/* arisc initialize succeeded */
ARISC_LOG("sunxi-arisc driver v%s startup succeeded\n", DRV_VERSION);
return 0;
}