void cpu_start_restore(void) { struct cpu_cluster *cc = (struct cpu_cluster *)__pa(&cpu_cluster); struct cpu *cp = (struct cpu *)__pa(&cpu); int *chip_ver = (int *)__pa(&e1_chip); #if 0 //wschen 2011-08-12 extern int armV7_perf_mon_is_overflow(unsigned int n); extern unsigned int armV7_perf_mon_get_cyc_cnt(void); extern void armV7_perf_mon_reset(void); extern void armV7_perf_mon_enable(unsigned int n); armV7_perf_mon_enable(0); armV7_perf_mon_reset(); armV7_perf_mon_enable(1); #endif if (*chip_ver) { volatile int i; for (i = 0; i < DELAY_COUNT; i++) { nop(); } if (cc->power_state == STATUS_DORMANT) { reg_write(IO_VIRT_TO_PHYS(SC_PWR_CON0), 0xE125); /* SRAM wake up */ } else { reg_write(IO_VIRT_TO_PHYS(SC_PWR_CON0), 0xC125); /* SRAM power up */ } dsb(); for (i = 0; i < DELAY_COUNT; i++) { nop(); } if (cc->power_state == STATUS_DORMANT) { reg_write(IO_VIRT_TO_PHYS(SC_PWR_CON2), 0xE525); /* SRAM wake up */ } else { reg_write(IO_VIRT_TO_PHYS(SC_PWR_CON2), 0xC525); /* SRAM power up */ } dsb(); for (i = 0; i < DELAY_COUNT; i++) { nop(); } } platform_restore_context(cc, cp); }
/* * mt65xx_mon_disable: Disable hardware monitors. * Return 0. */ int mt65xx_mon_disable(void) { // disable ARM performance monitors armV7_perf_mon_enable(0); // disable all L2C event counters mt65xx_reg_sync_writel(0, PL310_BASE + L2X0_EVENT_CNT_CTRL); BM_Pause(); return 0; }
/* * mt65xx_mon_enable: Enable hardware monitors. * Return 0. */ int mt65xx_mon_enable(void) { // reset all ARM monitor counters to 0 armV7_perf_mon_reset(); // enable ARM performance monitors armV7_perf_mon_enable(1); // reset and enable L2C event counters mt65xx_reg_sync_writel(7, PL310_BASE + L2X0_EVENT_CNT_CTRL); // stopping EMI monitors will reset all counters BM_Enable(0); // start EMI monitor counting BM_Enable(1); return 0; }