void board_init_f(ulong dummy) { lowlevel_clock_init(); #if !defined(CONFIG_WDT_AT91) at91_disable_wdt(); #endif /* * At this stage the main oscillator is supposed to be enabled * PCK = MCK = MOSC */ at91_pllicpr_init(0x00); /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ at91_plla_init(CONFIG_SYS_AT91_PLLA); /* PCK = PLLA = 2 * MCK */ at91_mck_init(CONFIG_SYS_MCKR); /* Switch MCK on PLLA output */ at91_mck_init(CONFIG_SYS_MCKR_CSS); #if defined(CONFIG_SYS_AT91_PLLB) /* Configure PLLB */ at91_pllb_init(CONFIG_SYS_AT91_PLLB); #endif /* Enable External Reset */ enable_ext_reset(); /* Initialize matrix */ matrix_init(); gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; /* * init timer long enough for using in spl. */ timer_init(); /* enable clocks for all PIOs */ #if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12) at91_periph_clk_enable(ATMEL_ID_PIOAB); at91_periph_clk_enable(ATMEL_ID_PIOCD); #else at91_periph_clk_enable(ATMEL_ID_PIOA); at91_periph_clk_enable(ATMEL_ID_PIOB); at91_periph_clk_enable(ATMEL_ID_PIOC); #endif #if defined(CONFIG_SPL_SERIAL_SUPPORT) /* init console */ at91_seriald_hw_init(); preloader_console_init(); #endif mem_init(); at91_spl_board_init(); }
void at91_pmc_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; u32 tmp; /* * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz * so we need to slow down and configure MCKR accordingly. * This is why we have a special flavor of the switching function. */ tmp = AT91_PMC_MCKR_PLLADIV_2 | AT91_PMC_MCKR_MDIV_3 | AT91_PMC_MCKR_CSS_MAIN; at91_mck_init_down(tmp); tmp = AT91_PMC_PLLAR_29 | AT91_PMC_PLLXR_PLLCOUNT(0x3f) | AT91_PMC_PLLXR_MUL(82) | AT91_PMC_PLLXR_DIV(1); at91_plla_init(tmp); writel(0x0 << 8, &pmc->pllicpr); tmp = AT91_PMC_MCKR_H32MXDIV | AT91_PMC_MCKR_PLLADIV_2 | AT91_PMC_MCKR_MDIV_3 | AT91_PMC_MCKR_CSS_PLLA; at91_mck_init(tmp); }
void at91_pmc_init(void) { u32 tmp; tmp = AT91_PMC_PLLAR_29 | AT91_PMC_PLLXR_PLLCOUNT(0x3f) | AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1); at91_plla_init(tmp); at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3)); tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA; at91_mck_init(tmp); }
void at91_pmc_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; u32 tmp; tmp = AT91_PMC_PLLAR_29 | AT91_PMC_PLLXR_PLLCOUNT(0x3f) | AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1); at91_plla_init(tmp); writel(0x3 << 8, &pmc->pllicpr); tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA; at91_mck_init(tmp); }
void at91_pmc_init(void) { u32 tmp; tmp = AT91_PMC_PLLAR_29 | AT91_PMC_PLLXR_PLLCOUNT(0x3f) | AT91_PMC_PLLXR_MUL(87) | AT91_PMC_PLLXR_DIV(1); at91_plla_init(tmp); at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0)); tmp = AT91_PMC_MCKR_H32MXDIV | AT91_PMC_MCKR_PLLADIV_2 | AT91_PMC_MCKR_MDIV_3 | AT91_PMC_MCKR_CSS_PLLA; at91_mck_init(tmp); }